Lines Matching refs:REGB_WR32
142 REGB_WR32(MTL_BUTTRESS_WP_REQ_PAYLOAD0, val); in ivpu_pll_cmd_send()
147 REGB_WR32(MTL_BUTTRESS_WP_REQ_PAYLOAD1, val); in ivpu_pll_cmd_send()
151 REGB_WR32(MTL_BUTTRESS_WP_REQ_PAYLOAD2, val); in ivpu_pll_cmd_send()
155 REGB_WR32(MTL_BUTTRESS_WP_REQ_CMD, val); in ivpu_pll_cmd_send()
620 REGB_WR32(MTL_BUTTRESS_VPU_D0I3_CONTROL, val); in ivpu_boot_d0i3_drive()
688 REGB_WR32(MTL_BUTTRESS_VPU_IP_RESET, val); in ivpu_hw_mtl_reset()
910 REGB_WR32(MTL_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_ENABLE_MASK); in ivpu_hw_mtl_irq_enable()
911 REGB_WR32(MTL_BUTTRESS_GLOBAL_INT_MASK, 0x0); in ivpu_hw_mtl_irq_enable()
916 REGB_WR32(MTL_BUTTRESS_GLOBAL_INT_MASK, 0x1); in ivpu_hw_mtl_irq_disable()
917 REGB_WR32(MTL_BUTTRESS_LOCAL_INT_MASK, BUTTRESS_IRQ_DISABLE_MASK); in ivpu_hw_mtl_irq_disable()
919 REGB_WR32(MTL_VPU_HOST_SS_FW_SOC_IRQ_EN, 0x0); in ivpu_hw_mtl_irq_disable()
985 REGB_WR32(MTL_BUTTRESS_GLOBAL_INT_MASK, 0x1); in ivpu_hw_mtl_irqb_handler()
992 REGB_WR32(MTL_BUTTRESS_ATS_ERR_CLEAR, 0x1); in ivpu_hw_mtl_irqb_handler()
1003 REGB_WR32(MTL_BUTTRESS_UFI_ERR_CLEAR, 0x1); in ivpu_hw_mtl_irqb_handler()
1012 REGB_WR32(MTL_BUTTRESS_INTERRUPT_STAT, 0x0); in ivpu_hw_mtl_irqb_handler()
1015 REGB_WR32(MTL_BUTTRESS_GLOBAL_INT_MASK, 0x0); in ivpu_hw_mtl_irqb_handler()