Lines Matching refs:REGV_WR32
264 REGV_WR32(MTL_VPU_HOST_SS_CPR_RST_CLR, val); in ivpu_boot_host_ss_rst_clr_assert()
281 REGV_WR32(MTL_VPU_HOST_SS_CPR_RST_SET, val); in ivpu_boot_host_ss_rst_drive()
298 REGV_WR32(MTL_VPU_HOST_SS_CPR_CLK_SET, val); in ivpu_boot_host_ss_clk_drive()
373 REGV_WR32(MTL_VPU_HOST_SS_AON_VPU_IDLE_GEN, 0x0); in ivpu_boot_vpu_idle_gen_disable()
386 REGV_WR32(MTL_VPU_HOST_SS_NOC_QREQN, val); in ivpu_boot_host_ss_axi_drive()
424 REGV_WR32(MTL_VPU_TOP_NOC_QREQN, val); in ivpu_boot_host_ss_top_noc_drive()
458 REGV_WR32(MTL_VPU_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, val); in ivpu_boot_pwr_island_trickle_drive()
470 REGV_WR32(MTL_VPU_HOST_SS_AON_PWR_ISLAND_EN0, val); in ivpu_boot_pwr_island_drive()
492 REGV_WR32(MTL_VPU_HOST_SS_AON_PWR_ISO_EN0, val); in ivpu_boot_pwr_island_isolation_drive()
504 REGV_WR32(MTL_VPU_HOST_SS_AON_DPU_ACTIVE, val); in ivpu_boot_dpu_active_drive()
552 REGV_WR32(MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES, val); in ivpu_boot_no_snoop_enable()
575 REGV_WR32(MTL_VPU_HOST_IF_TBU_MMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
586 REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in ivpu_boot_soc_cpu_boot()
589 REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in ivpu_boot_soc_cpu_boot()
592 REGV_WR32(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); in ivpu_boot_soc_cpu_boot()
595 REGV_WR32(MTL_VPU_HOST_SS_LOADING_ADDRESS_LO, val); in ivpu_boot_soc_cpu_boot()
598 REGV_WR32(MTL_VPU_HOST_SS_LOADING_ADDRESS_LO, val); in ivpu_boot_soc_cpu_boot()
834 REGV_WR32(MTL_VPU_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); in ivpu_hw_mtl_wdt_disable()
835 REGV_WR32(MTL_VPU_CPU_SS_TIM_WATCHDOG, TIM_WATCHDOG_RESET_VALUE); in ivpu_hw_mtl_wdt_disable()
838 REGV_WR32(MTL_VPU_CPU_SS_TIM_SAFE, TIM_SAFE_ENABLE); in ivpu_hw_mtl_wdt_disable()
839 REGV_WR32(MTL_VPU_CPU_SS_TIM_WDOG_EN, 0); in ivpu_hw_mtl_wdt_disable()
844 REGV_WR32(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, val); in ivpu_hw_mtl_wdt_disable()
898 REGV_WR32(MTL_VPU_CPU_SS_TIM_IPC_FIFO, vpu_addr); in ivpu_hw_mtl_reg_ipc_tx_set()
908 REGV_WR32(MTL_VPU_HOST_SS_FW_SOC_IRQ_EN, ITF_FIREWALL_VIOLATION_MASK); in ivpu_hw_mtl_irq_enable()
949 REGV_WR32(MTL_VPU_HOST_SS_ICB_CLEAR_0, status); in ivpu_hw_mtl_irqv_handler()