Lines Matching refs:REG_CLR_FLD
276 val = REG_CLR_FLD(MTL_VPU_HOST_SS_CPR_RST_SET, TOP_NOC, val); in ivpu_boot_host_ss_rst_drive()
277 val = REG_CLR_FLD(MTL_VPU_HOST_SS_CPR_RST_SET, DSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
278 val = REG_CLR_FLD(MTL_VPU_HOST_SS_CPR_RST_SET, MSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
293 val = REG_CLR_FLD(MTL_VPU_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in ivpu_boot_host_ss_clk_drive()
294 val = REG_CLR_FLD(MTL_VPU_HOST_SS_CPR_CLK_SET, DSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
295 val = REG_CLR_FLD(MTL_VPU_HOST_SS_CPR_CLK_SET, MSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
385 val = REG_CLR_FLD(MTL_VPU_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in ivpu_boot_host_ss_axi_drive()
421 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
422 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in ivpu_boot_host_ss_top_noc_drive()
456 val = REG_CLR_FLD(MTL_VPU_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); in ivpu_boot_pwr_island_trickle_drive()
468 val = REG_CLR_FLD(MTL_VPU_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); in ivpu_boot_pwr_island_drive()
490 val = REG_CLR_FLD(MTL_VPU_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in ivpu_boot_pwr_island_isolation_drive()
502 val = REG_CLR_FLD(MTL_VPU_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); in ivpu_boot_dpu_active_drive()
585 val = REG_CLR_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTVEC, val); in ivpu_boot_soc_cpu_boot()
591 val = REG_CLR_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); in ivpu_boot_soc_cpu_boot()
619 val = REG_CLR_FLD(MTL_BUTTRESS_VPU_D0I3_CONTROL, I3, val); in ivpu_boot_d0i3_drive()
843 val = REG_CLR_FLD(MTL_VPU_CPU_SS_TIM_GEN_CONFIG, WDOG_TO_INT_CLR, val); in ivpu_hw_mtl_wdt_disable()