Lines Matching refs:REG_SET_FLD
154 val = REG_SET_FLD(MTL_BUTTRESS_WP_REQ_CMD, SEND, val); in ivpu_pll_cmd_send()
260 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in ivpu_boot_host_ss_rst_clr_assert()
261 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in ivpu_boot_host_ss_rst_clr_assert()
262 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in ivpu_boot_host_ss_rst_clr_assert()
272 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_SET, TOP_NOC, val); in ivpu_boot_host_ss_rst_drive()
273 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_SET, DSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
274 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_SET, MSS_MAS, val); in ivpu_boot_host_ss_rst_drive()
289 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in ivpu_boot_host_ss_clk_drive()
290 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_CLK_SET, DSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
291 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_CLK_SET, MSS_MAS, val); in ivpu_boot_host_ss_clk_drive()
383 val = REG_SET_FLD(MTL_VPU_HOST_SS_NOC_QREQN, TOP_SOCMMIO, val); in ivpu_boot_host_ss_axi_drive()
418 val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
419 val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in ivpu_boot_host_ss_top_noc_drive()
454 val = REG_SET_FLD(MTL_VPU_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0, MSS_CPU, val); in ivpu_boot_pwr_island_trickle_drive()
466 val = REG_SET_FLD(MTL_VPU_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val); in ivpu_boot_pwr_island_drive()
488 val = REG_SET_FLD(MTL_VPU_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in ivpu_boot_pwr_island_isolation_drive()
500 val = REG_SET_FLD(MTL_VPU_HOST_SS_AON_DPU_ACTIVE, DPU_ACTIVE, val); in ivpu_boot_dpu_active_drive()
548 val = REG_SET_FLD(MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES, NOSNOOP_OVERRIDE_EN, val); in ivpu_boot_no_snoop_enable()
549 val = REG_SET_FLD(MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES, AW_NOSNOOP_OVERRIDE, val); in ivpu_boot_no_snoop_enable()
550 val = REG_SET_FLD(MTL_VPU_HOST_IF_TCU_PTW_OVERRIDES, AR_NOSNOOP_OVERRIDE, val); in ivpu_boot_no_snoop_enable()
560 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
561 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
562 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
563 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
565 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
566 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
567 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
568 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
569 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
570 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
571 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU3_AWMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
572 val = REG_SET_FLD(MTL_VPU_HOST_IF_TBU_MMUSSIDV, TBU3_ARMMUSSIDV, val); in ivpu_boot_tbu_mmu_enable()
583 val = REG_SET_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RSTRUN0, val); in ivpu_boot_soc_cpu_boot()
588 val = REG_SET_FLD(MTL_VPU_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); in ivpu_boot_soc_cpu_boot()
597 val = REG_SET_FLD(MTL_VPU_HOST_SS_LOADING_ADDRESS_LO, DONE, val); in ivpu_boot_soc_cpu_boot()
617 val = REG_SET_FLD(MTL_BUTTRESS_VPU_D0I3_CONTROL, I3, val); in ivpu_boot_d0i3_drive()
687 val = REG_SET_FLD(MTL_BUTTRESS_VPU_IP_RESET, TRIGGER, val); in ivpu_hw_mtl_reset()