Lines Matching refs:hpriv
438 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) argument
439 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) argument
440 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) argument
441 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) argument
442 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) argument
577 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
579 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
580 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
584 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
604 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
606 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
607 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
611 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
616 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
617 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
621 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
622 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
624 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
628 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
631 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
634 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
922 struct mv_host_priv *hpriv = host->private_data; in mv_host_base() local
923 return hpriv->base; in mv_host_base()
993 struct mv_host_priv *hpriv, in mv_set_edma_ptrs() argument
1023 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) in mv_write_main_irq_mask() argument
1037 writelfl(mask, hpriv->main_irq_mask_addr); in mv_write_main_irq_mask()
1043 struct mv_host_priv *hpriv = host->private_data; in mv_set_main_irq_mask() local
1046 old_mask = hpriv->main_irq_mask; in mv_set_main_irq_mask()
1049 hpriv->main_irq_mask = new_mask; in mv_set_main_irq_mask()
1050 mv_write_main_irq_mask(new_mask, hpriv); in mv_set_main_irq_mask()
1071 struct mv_host_priv *hpriv = ap->host->private_data; in mv_clear_and_enable_port_irqs() local
1085 if (IS_GEN_IIE(hpriv)) in mv_clear_and_enable_port_irqs()
1094 struct mv_host_priv *hpriv = host->private_data; in mv_set_irq_coalescing() local
1095 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_set_irq_coalescing()
1098 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; in mv_set_irq_coalescing()
1117 if (is_dual_hc && !IS_GEN_I(hpriv)) { in mv_set_irq_coalescing()
1174 struct mv_host_priv *hpriv = ap->host->private_data; in mv_start_edma() local
1178 mv_set_edma_ptrs(port_mmio, hpriv, pp); in mv_start_edma()
1358 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv_scr_write() local
1376 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { in mv_scr_write()
1505 struct mv_host_priv *hpriv = ap->host->private_data; in mv_60x1_errata_sata25() local
1509 old = readl(hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1515 writel(new, hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1559 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_enable() local
1563 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) in mv_soc_led_blink_enable()
1565 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_enable()
1574 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_disable() local
1579 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) in mv_soc_led_blink_disable()
1583 for (port = 0; port < hpriv->n_ports; port++) { in mv_soc_led_blink_disable()
1591 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_disable()
1601 struct mv_host_priv *hpriv = ap->host->private_data; in mv_edma_cfg() local
1609 if (IS_GEN_I(hpriv)) in mv_edma_cfg()
1612 else if (IS_GEN_II(hpriv)) { in mv_edma_cfg()
1616 } else if (IS_GEN_IIE(hpriv)) { in mv_edma_cfg()
1638 if (!IS_SOC(hpriv)) in mv_edma_cfg()
1641 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) in mv_edma_cfg()
1645 if (IS_SOC(hpriv)) { in mv_edma_cfg()
1663 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_free_dma_mem() local
1668 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); in mv_port_free_dma_mem()
1672 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); in mv_port_free_dma_mem()
1681 if (tag == 0 || !IS_GEN_I(hpriv)) in mv_port_free_dma_mem()
1682 dma_pool_free(hpriv->sg_tbl_pool, in mv_port_free_dma_mem()
1703 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_start() local
1713 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); in mv_port_start()
1717 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); in mv_port_start()
1722 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) in mv_port_start()
1729 if (tag == 0 || !IS_GEN_I(hpriv)) { in mv_port_start()
1730 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, in mv_port_start()
2400 struct mv_host_priv *hpriv = ap->host->private_data; in mv_qc_issue() local
2412 if (IS_GEN_II(hpriv)) in mv_qc_issue()
2639 struct mv_host_priv *hpriv = ap->host->private_data; in mv_err_intr() local
2654 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { in mv_err_intr()
2674 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { in mv_err_intr()
2711 if (IS_GEN_I(hpriv)) { in mv_err_intr()
2799 struct mv_host_priv *hpriv = ap->host->private_data; in mv_process_crpb_entries() local
2816 if (IS_GEN_I(hpriv)) { in mv_process_crpb_entries()
2882 struct mv_host_priv *hpriv = host->private_data; in mv_host_intr() local
2883 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_host_intr()
2890 for (port = 0; port < hpriv->n_ports; port++) { in mv_host_intr()
2925 if ((port + p) >= hpriv->n_ports) in mv_host_intr()
2947 struct mv_host_priv *hpriv = host->private_data; in mv_pci_error() local
2954 err_cause = readl(mmio + hpriv->irq_cause_offset); in mv_pci_error()
2961 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_pci_error()
3002 struct mv_host_priv *hpriv = host->private_data; in mv_interrupt() local
3004 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; in mv_interrupt()
3011 mv_write_main_irq_mask(0, hpriv); in mv_interrupt()
3013 main_irq_cause = readl(hpriv->main_irq_cause_addr); in mv_interrupt()
3014 pending_irqs = main_irq_cause & hpriv->main_irq_mask; in mv_interrupt()
3020 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) in mv_interrupt()
3021 handled = mv_pci_error(host, hpriv->base); in mv_interrupt()
3028 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); in mv_interrupt()
3054 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_read() local
3055 void __iomem *mmio = hpriv->base; in mv5_scr_read()
3068 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_write() local
3069 void __iomem *mmio = hpriv->base; in mv5_scr_write()
3096 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) in mv5_reset_flash() argument
3101 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, in mv5_read_preamp() argument
3109 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ in mv5_read_preamp()
3110 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ in mv5_read_preamp()
3113 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) in mv5_enable_leds() argument
3126 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, in mv5_phy_errata() argument
3132 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); in mv5_phy_errata()
3147 tmp |= hpriv->signal[port].pre; in mv5_phy_errata()
3148 tmp |= hpriv->signal[port].amps; in mv5_phy_errata()
3155 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, in mv5_reset_hc_port() argument
3160 mv_reset_channel(hpriv, mmio, port); in mv5_reset_hc_port()
3179 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, in mv5_reset_one_hc() argument
3200 struct mv_host_priv *hpriv = host->private_data; in mv5_reset_hc() local
3205 mv5_reset_hc_port(hpriv, mmio, in mv5_reset_hc()
3208 mv5_reset_one_hc(hpriv, mmio, hc); in mv5_reset_hc()
3218 struct mv_host_priv *hpriv = host->private_data; in mv_reset_pci_bus() local
3229 ZERO(hpriv->irq_cause_offset); in mv_reset_pci_bus()
3230 ZERO(hpriv->irq_mask_offset); in mv_reset_pci_bus()
3238 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) in mv6_reset_flash() argument
3242 mv5_reset_flash(hpriv, mmio); in mv6_reset_flash()
3314 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, in mv6_read_preamp() argument
3322 hpriv->signal[idx].amps = 0x7 << 8; in mv6_read_preamp()
3323 hpriv->signal[idx].pre = 0x1 << 5; in mv6_read_preamp()
3330 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv6_read_preamp()
3331 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv6_read_preamp()
3334 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) in mv6_enable_leds() argument
3339 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, in mv6_phy_errata() argument
3344 u32 hp_flags = hpriv->hp_flags; in mv6_phy_errata()
3374 if (IS_SOC(hpriv)) in mv6_phy_errata()
3384 if (IS_GEN_IIE(hpriv)) in mv6_phy_errata()
3402 m2 |= hpriv->signal[port].amps; in mv6_phy_errata()
3403 m2 |= hpriv->signal[port].pre; in mv6_phy_errata()
3407 if (IS_GEN_IIE(hpriv)) { in mv6_phy_errata()
3417 static void mv_soc_enable_leds(struct mv_host_priv *hpriv, in mv_soc_enable_leds() argument
3423 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, in mv_soc_read_preamp() argument
3432 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv_soc_read_preamp()
3433 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv_soc_read_preamp()
3438 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, in mv_soc_reset_hc_port() argument
3443 mv_reset_channel(hpriv, mmio, port); in mv_soc_reset_hc_port()
3463 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, in mv_soc_reset_one_hc() argument
3479 struct mv_host_priv *hpriv = host->private_data; in mv_soc_reset_hc() local
3482 for (port = 0; port < hpriv->n_ports; port++) in mv_soc_reset_hc()
3483 mv_soc_reset_hc_port(hpriv, mmio, port); in mv_soc_reset_hc()
3485 mv_soc_reset_one_hc(hpriv, mmio); in mv_soc_reset_hc()
3490 static void mv_soc_reset_flash(struct mv_host_priv *hpriv, in mv_soc_reset_flash() argument
3501 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, in mv_soc_65n_phy_errata() argument
3539 static bool soc_is_65n(struct mv_host_priv *hpriv) in soc_is_65n() argument
3541 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); in soc_is_65n()
3558 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, in mv_reset_channel() argument
3571 if (!IS_GEN_I(hpriv)) { in mv_reset_channel()
3584 hpriv->ops->phy_errata(hpriv, mmio, port_no); in mv_reset_channel()
3586 if (IS_GEN_I(hpriv)) in mv_reset_channel()
3622 struct mv_host_priv *hpriv = ap->host->private_data; in mv_hardreset() local
3624 void __iomem *mmio = hpriv->base; in mv_hardreset()
3629 mv_reset_channel(hpriv, mmio, ap->port_no); in mv_hardreset()
3645 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { in mv_hardreset()
3666 struct mv_host_priv *hpriv = ap->host->private_data; in mv_eh_thaw() local
3669 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); in mv_eh_thaw()
3725 struct mv_host_priv *hpriv = host->private_data; in mv_in_pcix_mode() local
3726 void __iomem *mmio = hpriv->base; in mv_in_pcix_mode()
3729 if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) in mv_in_pcix_mode()
3739 struct mv_host_priv *hpriv = host->private_data; in mv_pci_cut_through_okay() local
3740 void __iomem *mmio = hpriv->base; in mv_pci_cut_through_okay()
3753 struct mv_host_priv *hpriv = host->private_data; in mv_60x1b2_errata_pci7() local
3754 void __iomem *mmio = hpriv->base; in mv_60x1b2_errata_pci7()
3766 struct mv_host_priv *hpriv = host->private_data; in mv_chip_id() local
3767 u32 hp_flags = hpriv->hp_flags; in mv_chip_id()
3771 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3791 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3811 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3863 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3880 if (soc_is_65n(hpriv)) in mv_chip_id()
3881 hpriv->ops = &mv_soc_65n_ops; in mv_chip_id()
3883 hpriv->ops = &mv_soc_ops; in mv_chip_id()
3893 hpriv->hp_flags = hp_flags; in mv_chip_id()
3895 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; in mv_chip_id()
3896 hpriv->irq_mask_offset = PCIE_IRQ_MASK; in mv_chip_id()
3897 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; in mv_chip_id()
3899 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; in mv_chip_id()
3900 hpriv->irq_mask_offset = PCI_IRQ_MASK; in mv_chip_id()
3901 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; in mv_chip_id()
3920 struct mv_host_priv *hpriv = host->private_data; in mv_init_host() local
3921 void __iomem *mmio = hpriv->base; in mv_init_host()
3923 rc = mv_chip_id(host, hpriv->board_idx); in mv_init_host()
3927 if (IS_SOC(hpriv)) { in mv_init_host()
3928 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3929 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; in mv_init_host()
3931 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3932 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; in mv_init_host()
3936 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); in mv_init_host()
3944 if (hpriv->ops->read_preamp) in mv_init_host()
3945 hpriv->ops->read_preamp(hpriv, port, mmio); in mv_init_host()
3947 rc = hpriv->ops->reset_hc(host, mmio, n_hc); in mv_init_host()
3951 hpriv->ops->reset_flash(hpriv, mmio); in mv_init_host()
3952 hpriv->ops->reset_bus(host, mmio); in mv_init_host()
3953 hpriv->ops->enable_leds(hpriv, mmio); in mv_init_host()
3974 if (!IS_SOC(hpriv)) { in mv_init_host()
3976 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_init_host()
3979 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); in mv_init_host()
3993 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) in mv_create_dma_pools() argument
3995 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, in mv_create_dma_pools()
3997 if (!hpriv->crqb_pool) in mv_create_dma_pools()
4000 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, in mv_create_dma_pools()
4002 if (!hpriv->crpb_pool) in mv_create_dma_pools()
4005 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, in mv_create_dma_pools()
4007 if (!hpriv->sg_tbl_pool) in mv_create_dma_pools()
4013 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, in mv_conf_mbus_windows() argument
4019 writel(0, hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4020 writel(0, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4029 hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
4030 writel(cs->base, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4049 struct mv_host_priv *hpriv; in mv_platform_probe() local
4100 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_platform_probe()
4102 if (!host || !hpriv) in mv_platform_probe()
4104 hpriv->port_clks = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4107 if (!hpriv->port_clks) in mv_platform_probe()
4109 hpriv->port_phys = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4112 if (!hpriv->port_phys) in mv_platform_probe()
4114 host->private_data = hpriv; in mv_platform_probe()
4115 hpriv->board_idx = chip_soc; in mv_platform_probe()
4118 hpriv->base = devm_ioremap(&pdev->dev, res->start, in mv_platform_probe()
4120 if (!hpriv->base) in mv_platform_probe()
4123 hpriv->base -= SATAHC0_REG_BASE; in mv_platform_probe()
4125 hpriv->clk = clk_get(&pdev->dev, NULL); in mv_platform_probe()
4126 if (IS_ERR(hpriv->clk)) in mv_platform_probe()
4129 clk_prepare_enable(hpriv->clk); in mv_platform_probe()
4134 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); in mv_platform_probe()
4135 if (!IS_ERR(hpriv->port_clks[port])) in mv_platform_probe()
4136 clk_prepare_enable(hpriv->port_clks[port]); in mv_platform_probe()
4139 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, in mv_platform_probe()
4141 if (IS_ERR(hpriv->port_phys[port])) { in mv_platform_probe()
4142 rc = PTR_ERR(hpriv->port_phys[port]); in mv_platform_probe()
4143 hpriv->port_phys[port] = NULL; in mv_platform_probe()
4148 hpriv->n_ports = port; in mv_platform_probe()
4151 phy_power_on(hpriv->port_phys[port]); in mv_platform_probe()
4155 hpriv->n_ports = n_ports; in mv_platform_probe()
4162 mv_conf_mbus_windows(hpriv, dram); in mv_platform_probe()
4164 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_platform_probe()
4175 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; in mv_platform_probe()
4190 if (!IS_ERR(hpriv->clk)) { in mv_platform_probe()
4191 clk_disable_unprepare(hpriv->clk); in mv_platform_probe()
4192 clk_put(hpriv->clk); in mv_platform_probe()
4194 for (port = 0; port < hpriv->n_ports; port++) { in mv_platform_probe()
4195 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_probe()
4196 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_probe()
4197 clk_put(hpriv->port_clks[port]); in mv_platform_probe()
4199 phy_power_off(hpriv->port_phys[port]); in mv_platform_probe()
4216 struct mv_host_priv *hpriv = host->private_data; in mv_platform_remove() local
4220 if (!IS_ERR(hpriv->clk)) { in mv_platform_remove()
4221 clk_disable_unprepare(hpriv->clk); in mv_platform_remove()
4222 clk_put(hpriv->clk); in mv_platform_remove()
4225 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_remove()
4226 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_remove()
4227 clk_put(hpriv->port_clks[port]); in mv_platform_remove()
4229 phy_power_off(hpriv->port_phys[port]); in mv_platform_remove()
4251 struct mv_host_priv *hpriv = host->private_data; in mv_platform_resume() local
4258 mv_conf_mbus_windows(hpriv, dram); in mv_platform_resume()
4329 struct mv_host_priv *hpriv = host->private_data; in mv_print_info() local
4344 if (IS_GEN_I(hpriv)) in mv_print_info()
4346 else if (IS_GEN_II(hpriv)) in mv_print_info()
4348 else if (IS_GEN_IIE(hpriv)) in mv_print_info()
4355 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); in mv_print_info()
4372 struct mv_host_priv *hpriv; in mv_pci_init_one() local
4381 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_pci_init_one()
4382 if (!host || !hpriv) in mv_pci_init_one()
4384 host->private_data = hpriv; in mv_pci_init_one()
4385 hpriv->n_ports = n_ports; in mv_pci_init_one()
4386 hpriv->board_idx = board_idx; in mv_pci_init_one()
4399 hpriv->base = host->iomap[MV_PRIMARY_BAR]; in mv_pci_init_one()
4407 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_pci_init_one()
4413 void __iomem *port_mmio = mv_port_base(hpriv->base, port); in mv_pci_init_one()
4414 unsigned int offset = port_mmio - hpriv->base; in mv_pci_init_one()
4427 hpriv->hp_flags |= MV_HP_FLAG_MSI; in mv_pci_init_one()
4435 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); in mv_pci_init_one()