Lines Matching refs:endpoint
90 static void malformed_message(struct xilly_endpoint *endpoint, u32 *buf) in malformed_message() argument
101 dev_warn(endpoint->dev, in malformed_message()
499 channel->endpoint = ep; in xilly_setupchannels()
589 static int xilly_scan_idt(struct xilly_endpoint *endpoint, in xilly_scan_idt() argument
593 unsigned char *idt = endpoint->channels[1]->wr_buffers[0]->addr; in xilly_scan_idt()
594 unsigned char *end_of_idt = idt + endpoint->idtlen - 4; in xilly_scan_idt()
612 dev_err(endpoint->dev, in xilly_scan_idt()
618 len = endpoint->idtlen - (3 + ((int) (scan - idt))); in xilly_scan_idt()
621 dev_err(endpoint->dev, in xilly_scan_idt()
627 endpoint->num_channels = count; in xilly_scan_idt()
632 static int xilly_obtain_idt(struct xilly_endpoint *endpoint) in xilly_obtain_idt() argument
638 channel = endpoint->channels[1]; /* This should be generated ad-hoc */ in xilly_obtain_idt()
644 endpoint->registers + fpga_buf_ctrl_reg); in xilly_obtain_idt()
651 dev_err(endpoint->dev, "Failed to obtain IDT. Aborting.\n"); in xilly_obtain_idt()
653 if (endpoint->fatal_error) in xilly_obtain_idt()
659 dma_sync_single_for_cpu(channel->endpoint->dev, in xilly_obtain_idt()
664 if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) { in xilly_obtain_idt()
665 dev_err(endpoint->dev, in xilly_obtain_idt()
667 channel->wr_buffers[0]->end_offset, endpoint->idtlen); in xilly_obtain_idt()
672 endpoint->idtlen+1) != 0) { in xilly_obtain_idt()
673 dev_err(endpoint->dev, "IDT failed CRC check. Aborting.\n"); in xilly_obtain_idt()
681 dev_err(endpoint->dev, in xilly_obtain_idt()
706 if (channel->endpoint->fatal_error) in xillybus_read()
773 dma_sync_single_for_cpu(channel->endpoint->dev, in xillybus_read()
788 dma_sync_single_for_device(channel->endpoint->dev, in xillybus_read()
803 channel->endpoint->registers + in xillybus_read()
885 mutex_lock(&channel->endpoint->register_mutex); in xillybus_read()
888 channel->endpoint->registers + in xillybus_read()
894 channel->endpoint->registers + in xillybus_read()
897 mutex_unlock(&channel->endpoint-> in xillybus_read()
932 if (channel->endpoint->fatal_error) in xillybus_read()
961 if (channel->endpoint->fatal_error) in xillybus_read()
983 channel->endpoint->registers + in xillybus_read()
998 if (channel->endpoint->fatal_error) in xillybus_read()
1025 if (channel->endpoint->fatal_error) in xillybus_myflush()
1091 dma_sync_single_for_device(channel->endpoint->dev, in xillybus_myflush()
1096 mutex_lock(&channel->endpoint->register_mutex); in xillybus_myflush()
1099 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_myflush()
1104 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_myflush()
1106 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_myflush()
1155 dev_warn(channel->endpoint->dev, in xillybus_myflush()
1171 if (channel->endpoint->fatal_error) in xillybus_myflush()
1195 dev_warn(channel->endpoint->dev, in xillybus_autoflush()
1198 dev_err(channel->endpoint->dev, in xillybus_autoflush()
1216 if (channel->endpoint->fatal_error) in xillybus_write()
1310 dma_sync_single_for_cpu(channel->endpoint->dev, in xillybus_write()
1331 dma_sync_single_for_device(channel->endpoint->dev, in xillybus_write()
1336 mutex_lock(&channel->endpoint->register_mutex); in xillybus_write()
1339 channel->endpoint->registers + in xillybus_write()
1345 channel->endpoint->registers + in xillybus_write()
1348 mutex_unlock(&channel->endpoint-> in xillybus_write()
1358 if (channel->endpoint->fatal_error) in xillybus_write()
1395 if (channel->endpoint->fatal_error) in xillybus_write()
1411 if (channel->endpoint->fatal_error) in xillybus_write()
1431 struct xilly_endpoint *endpoint; in xillybus_open() local
1435 rc = xillybus_find_inode(inode, (void **)&endpoint, &index); in xillybus_open()
1439 if (endpoint->fatal_error) in xillybus_open()
1442 channel = endpoint->channels[1 + index]; in xillybus_open()
1460 dev_err(endpoint->dev, in xillybus_open()
1467 dev_err(endpoint->dev, in xillybus_open()
1523 channel->endpoint->registers + in xillybus_open()
1544 channel->endpoint->registers + in xillybus_open()
1572 if (channel->endpoint->fatal_error) in xillybus_release()
1588 channel->endpoint->registers + in xillybus_release()
1602 channel->endpoint->registers + in xillybus_release()
1652 dev_warn(channel->endpoint->dev, in xillybus_release()
1678 if (channel->endpoint->fatal_error) in xillybus_llseek()
1705 mutex_lock(&channel->endpoint->register_mutex); in xillybus_llseek()
1708 channel->endpoint->registers + fpga_buf_offset_reg); in xillybus_llseek()
1712 channel->endpoint->registers + fpga_buf_ctrl_reg); in xillybus_llseek()
1714 mutex_unlock(&channel->endpoint->register_mutex); in xillybus_llseek()
1745 poll_wait(filp, &channel->endpoint->ep_wait, wait); in xillybus_poll()
1788 if (channel->endpoint->fatal_error) in xillybus_poll()
1807 struct xilly_endpoint *endpoint; in xillybus_init_endpoint() local
1809 endpoint = devm_kzalloc(dev, sizeof(*endpoint), GFP_KERNEL); in xillybus_init_endpoint()
1810 if (!endpoint) in xillybus_init_endpoint()
1813 endpoint->dev = dev; in xillybus_init_endpoint()
1814 endpoint->msg_counter = 0x0b; in xillybus_init_endpoint()
1815 endpoint->failed_messages = 0; in xillybus_init_endpoint()
1816 endpoint->fatal_error = 0; in xillybus_init_endpoint()
1818 init_waitqueue_head(&endpoint->ep_wait); in xillybus_init_endpoint()
1819 mutex_init(&endpoint->register_mutex); in xillybus_init_endpoint()
1821 return endpoint; in xillybus_init_endpoint()
1825 static int xilly_quiesce(struct xilly_endpoint *endpoint) in xilly_quiesce() argument
1829 endpoint->idtlen = -1; in xilly_quiesce()
1831 iowrite32((u32) (endpoint->dma_using_dac & 0x0001), in xilly_quiesce()
1832 endpoint->registers + fpga_dma_control_reg); in xilly_quiesce()
1834 t = wait_event_interruptible_timeout(endpoint->ep_wait, in xilly_quiesce()
1835 (endpoint->idtlen >= 0), in xilly_quiesce()
1838 dev_err(endpoint->dev, in xilly_quiesce()
1845 int xillybus_endpoint_discovery(struct xilly_endpoint *endpoint) in xillybus_endpoint_discovery() argument
1852 struct device *dev = endpoint->dev; in xillybus_endpoint_discovery()
1871 iowrite32(1, endpoint->registers + fpga_endian_reg); in xillybus_endpoint_discovery()
1879 endpoint->num_channels = 0; in xillybus_endpoint_discovery()
1881 rc = xilly_setupchannels(endpoint, bogus_idt, 1); in xillybus_endpoint_discovery()
1886 iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg); in xillybus_endpoint_discovery()
1888 endpoint->idtlen = -1; in xillybus_endpoint_discovery()
1894 iowrite32((u32) (endpoint->dma_using_dac & 0x0001), in xillybus_endpoint_discovery()
1895 endpoint->registers + fpga_dma_control_reg); in xillybus_endpoint_discovery()
1897 t = wait_event_interruptible_timeout(endpoint->ep_wait, in xillybus_endpoint_discovery()
1898 (endpoint->idtlen >= 0), in xillybus_endpoint_discovery()
1901 dev_err(endpoint->dev, "No response from FPGA. Aborting.\n"); in xillybus_endpoint_discovery()
1906 iowrite32((u32) (0x0002 | (endpoint->dma_using_dac & 0x0001)), in xillybus_endpoint_discovery()
1907 endpoint->registers + fpga_dma_control_reg); in xillybus_endpoint_discovery()
1910 while (endpoint->idtlen >= idtbuffersize) { in xillybus_endpoint_discovery()
1915 endpoint->num_channels = 1; in xillybus_endpoint_discovery()
1917 rc = xilly_setupchannels(endpoint, bogus_idt, 2); in xillybus_endpoint_discovery()
1921 rc = xilly_obtain_idt(endpoint); in xillybus_endpoint_discovery()
1925 rc = xilly_scan_idt(endpoint, &idt_handle); in xillybus_endpoint_discovery()
1933 rc = xilly_setupchannels(endpoint, in xillybus_endpoint_discovery()
1940 endpoint->owner, endpoint, in xillybus_endpoint_discovery()
1943 endpoint->num_channels, in xillybus_endpoint_discovery()
1954 xilly_quiesce(endpoint); in xillybus_endpoint_discovery()
1961 void xillybus_endpoint_remove(struct xilly_endpoint *endpoint) in xillybus_endpoint_remove() argument
1963 xillybus_cleanup_chrdev(endpoint, endpoint->dev); in xillybus_endpoint_remove()
1965 xilly_quiesce(endpoint); in xillybus_endpoint_remove()