Lines Matching refs:cg
81 void (*init_periph)(struct clockgen *cg);
102 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg) in cg_out() argument
104 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_out()
110 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg) in cg_in() argument
114 if (cg->info.flags & CG_LITTLE_ENDIAN) in cg_in()
469 static void __init p2041_init_periph(struct clockgen *cg) in p2041_init_periph() argument
473 reg = ioread32be(&cg->guts->rcwsr[7]); in p2041_init_periph()
476 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; in p2041_init_periph()
478 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p2041_init_periph()
481 static void __init p4080_init_periph(struct clockgen *cg) in p4080_init_periph() argument
485 reg = ioread32be(&cg->guts->rcwsr[7]); in p4080_init_periph()
488 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
490 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
493 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; in p4080_init_periph()
495 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p4080_init_periph()
498 static void __init p5020_init_periph(struct clockgen *cg) in p5020_init_periph() argument
503 reg = ioread32be(&cg->guts->rcwsr[7]); in p5020_init_periph()
508 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk; in p5020_init_periph()
510 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5020_init_periph()
513 static void __init p5040_init_periph(struct clockgen *cg) in p5040_init_periph() argument
518 reg = ioread32be(&cg->guts->rcwsr[7]); in p5040_init_periph()
523 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
525 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
528 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk; in p5040_init_periph()
530 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; in p5040_init_periph()
533 static void __init t1023_init_periph(struct clockgen *cg) in t1023_init_periph() argument
535 cg->fman[0] = cg->hwaccel[1]; in t1023_init_periph()
538 static void __init t1040_init_periph(struct clockgen *cg) in t1040_init_periph() argument
540 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk; in t1040_init_periph()
543 static void __init t2080_init_periph(struct clockgen *cg) in t2080_init_periph() argument
545 cg->fman[0] = cg->hwaccel[0]; in t2080_init_periph()
548 static void __init t4240_init_periph(struct clockgen *cg) in t4240_init_periph() argument
550 cg->fman[0] = cg->hwaccel[3]; in t4240_init_periph()
551 cg->fman[1] = cg->hwaccel[4]; in t4240_init_periph()
837 struct clockgen *cg; member
858 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
869 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
893 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg, in get_pll_div() argument
905 return &cg->pll[pll].div[div]; in get_pll_div()
908 static struct clk * __init create_mux_common(struct clockgen *cg, in create_mux_common() argument
930 div = get_pll_div(cg, hwc, i); in create_mux_common()
956 hwc->cg = cg; in create_mux_common()
969 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx) in create_one_cmux() argument
981 if (cg->info.flags & CG_VER3) in create_one_cmux()
982 hwc->reg = cg->regs + 0x70000 + 0x20 * idx; in create_one_cmux()
984 hwc->reg = cg->regs + 0x20 * idx; in create_one_cmux()
986 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]]; in create_one_cmux()
995 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in create_one_cmux()
996 div = get_pll_div(cg, hwc, clksel); in create_one_cmux()
1006 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk); in create_one_cmux()
1008 if (cg->info.flags & CG_CMUX_GE_PLAT) in create_one_cmux()
1013 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate, in create_one_cmux()
1017 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx) in create_one_hwaccel() argument
1025 hwc->reg = cg->regs + 0x20 * idx + 0x10; in create_one_hwaccel()
1026 hwc->info = cg->info.hwaccel[idx]; in create_one_hwaccel()
1028 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0, in create_one_hwaccel()
1032 static void __init create_muxes(struct clockgen *cg) in create_muxes() argument
1036 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) { in create_muxes()
1037 if (cg->info.cmux_to_group[i] < 0) in create_muxes()
1039 if (cg->info.cmux_to_group[i] >= in create_muxes()
1040 ARRAY_SIZE(cg->info.cmux_groups)) { in create_muxes()
1045 cg->cmux[i] = create_one_cmux(cg, i); in create_muxes()
1048 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) { in create_muxes()
1049 if (!cg->info.hwaccel[i]) in create_muxes()
1052 cg->hwaccel[i] = create_one_hwaccel(cg, i); in create_muxes()
1210 static void __init create_one_pll(struct clockgen *cg, int idx) in create_one_pll() argument
1214 struct clockgen_pll *pll = &cg->pll[idx]; in create_one_pll()
1218 if (!(cg->info.pll_mask & (1 << idx))) in create_one_pll()
1221 if (cg->coreclk && idx != PLATFORM_PLL) { in create_one_pll()
1222 if (IS_ERR(cg->coreclk)) in create_one_pll()
1228 if (cg->info.flags & CG_VER3) { in create_one_pll()
1231 reg = cg->regs + 0x60080; in create_one_pll()
1234 reg = cg->regs + 0x80; in create_one_pll()
1237 reg = cg->regs + 0xa0; in create_one_pll()
1240 reg = cg->regs + 0x10080; in create_one_pll()
1243 reg = cg->regs + 0x100a0; in create_one_pll()
1251 reg = cg->regs + 0xc00; in create_one_pll()
1253 reg = cg->regs + 0x800 + 0x20 * (idx - 1); in create_one_pll()
1257 mult = cg_in(cg, reg); in create_one_pll()
1265 if ((cg->info.flags & CG_VER3) || in create_one_pll()
1266 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL)) in create_one_pll()
1302 static void __init create_plls(struct clockgen *cg) in create_plls() argument
1306 for (i = 0; i < ARRAY_SIZE(cg->pll); i++) in create_plls()
1307 create_one_pll(cg, i); in create_plls()
1388 struct clockgen *cg = data; in clockgen_clk_get() local
1405 clk = cg->sysclk; in clockgen_clk_get()
1408 if (idx >= ARRAY_SIZE(cg->cmux)) in clockgen_clk_get()
1410 clk = cg->cmux[idx]; in clockgen_clk_get()
1413 if (idx >= ARRAY_SIZE(cg->hwaccel)) in clockgen_clk_get()
1415 clk = cg->hwaccel[idx]; in clockgen_clk_get()
1418 if (idx >= ARRAY_SIZE(cg->fman)) in clockgen_clk_get()
1420 clk = cg->fman[idx]; in clockgen_clk_get()
1423 pll = &cg->pll[PLATFORM_PLL]; in clockgen_clk_get()
1431 clk = cg->coreclk; in clockgen_clk_get()