Lines Matching refs:div_frc
173 u32 div_frc; member
434 u32 div_int, div_frc; in vc5_pll_recalc_rate() local
440 div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; in vc5_pll_recalc_rate()
443 return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); in vc5_pll_recalc_rate()
452 u64 div_frc; in vc5_pll_round_rate() local
462 div_frc = rate % *parent_rate; in vc5_pll_round_rate()
463 div_frc *= BIT(24) - 1; in vc5_pll_round_rate()
464 do_div(div_frc, *parent_rate); in vc5_pll_round_rate()
467 hwdata->div_frc = (u32)div_frc; in vc5_pll_round_rate()
469 return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); in vc5_pll_round_rate()
481 fb[2] = hwdata->div_frc >> 16; in vc5_pll_set_rate()
482 fb[3] = hwdata->div_frc >> 8; in vc5_pll_set_rate()
483 fb[4] = hwdata->div_frc; in vc5_pll_set_rate()
501 u32 div_int, div_frc; in vc5_fod_recalc_rate() local
511 div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | in vc5_fod_recalc_rate()
515 if (div_int == 0 && div_frc == 0) in vc5_fod_recalc_rate()
519 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); in vc5_fod_recalc_rate()
529 u64 div_frc; in vc5_fod_round_rate() local
544 div_frc = f_in % rate; in vc5_fod_round_rate()
545 div_frc <<= 24; in vc5_fod_round_rate()
546 do_div(div_frc, rate); in vc5_fod_round_rate()
549 hwdata->div_frc = (u32)div_frc; in vc5_fod_round_rate()
551 return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc); in vc5_fod_round_rate()
560 hwdata->div_frc >> 22, hwdata->div_frc >> 14, in vc5_fod_set_rate()
561 hwdata->div_frc >> 6, hwdata->div_frc << 2, in vc5_fod_set_rate()