Lines Matching refs:div2
456 int div1, div2; in wm8750_find_pll_bits() local
463 for (div2 = 7; div2 >= 0; div2--) in wm8750_find_pll_bits()
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
474 *divisor2 = div2; in wm8750_find_pll_bits()
482 *divisor2 = div2; in wm8750_find_pll_bits()
504 int div1, div2; in wm8850_find_pll_bits() local
511 for (div2 = 3; div2 >= 0; div2--) in wm8850_find_pll_bits()
514 ((div1 + 1) * (1 << div2)); in wm8850_find_pll_bits()
522 *divisor2 = div2; in wm8850_find_pll_bits()
530 *divisor2 = div2; in wm8850_find_pll_bits()
550 u32 filter, mul, div1, div2; in vtwm_pll_set_rate() local
564 ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); in vtwm_pll_set_rate()
566 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2); in vtwm_pll_set_rate()
569 ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2); in vtwm_pll_set_rate()
571 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2); in vtwm_pll_set_rate()
574 ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); in vtwm_pll_set_rate()
576 pll_val = WM8850_BITS_TO_VAL(mul, div1, div2); in vtwm_pll_set_rate()
601 u32 filter, mul, div1, div2; in vtwm_pll_round_rate() local
612 ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); in vtwm_pll_round_rate()
614 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()
617 ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); in vtwm_pll_round_rate()
619 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()
622 ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2); in vtwm_pll_round_rate()
624 round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2); in vtwm_pll_round_rate()