Lines Matching refs:shift
111 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ argument
112 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
120 #define imx_clk_divider(name, parent, reg, shift, width) \ argument
121 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
123 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \ argument
124 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
126 #define imx_clk_gate(name, parent, reg, shift) \ argument
127 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
129 #define imx_clk_gate_dis(name, parent, reg, shift) \ argument
130 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
132 #define imx_clk_gate2(name, parent, reg, shift) \ argument
133 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
135 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \ argument
136 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
138 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ argument
139 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
141 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \ argument
142 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
144 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
145 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
147 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
148 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
156 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
157 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
159 #define imx_clk_hw_gate(name, parent, reg, shift) \ argument
160 imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
162 #define imx_clk_hw_gate2(name, parent, reg, shift) \ argument
163 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
165 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \ argument
166 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
168 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \ argument
169 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
171 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \ argument
172 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
174 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \ argument
175 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
177 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \ argument
178 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
180 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \ argument
181 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
183 #define imx_clk_hw_gate3(name, parent, reg, shift) \ argument
184 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
186 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \ argument
187 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
189 #define imx_clk_hw_gate4(name, parent, reg, shift) \ argument
190 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
192 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \ argument
193 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
195 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \ argument
196 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
198 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \ argument
199 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
201 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
202 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
204 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \ argument
205 …__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_…
207 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \ argument
208 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
210 #define imx_clk_hw_divider(name, parent, reg, shift, width) \ argument
211 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
213 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \ argument
214 __imx_clk_hw_divider(name, parent, reg, shift, width, \
217 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \ argument
218 __imx_clk_hw_divider(name, parent, reg, shift, width, flags)
297 void __iomem *reg, u8 shift, u32 exclusive_mask);
306 void __iomem *reg, u8 shift, u8 width,
309 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
326 void __iomem *reg, u8 shift, u8 width,
330 u8 shift, u8 width, const char * const *parents,
354 void __iomem *reg, u8 shift, in __imx_clk_hw_divider() argument
358 reg, shift, width, 0, &imx_ccm_lock); in __imx_clk_hw_divider()
362 void __iomem *reg, u8 shift, in __imx_clk_hw_gate() argument
367 shift, clk_gate_flags, &imx_ccm_lock); in __imx_clk_hw_gate()
371 void __iomem *reg, u8 shift, u8 cgr_val, in __imx_clk_hw_gate2() argument
376 shift, cgr_val, 0x3, 0, &imx_ccm_lock, share_count); in __imx_clk_hw_gate2()
380 u8 shift, u8 width, const char * const *parents, in __imx_clk_hw_mux() argument
384 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, in __imx_clk_hw_mux()
461 unsigned long flags, void __iomem *reg, u8 shift, u8 width,