Lines Matching refs:clk_info
83 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_recalc_rate() local
90 BUG_ON(clk_info->type != CGU_CLK_PLL); in ingenic_pll_recalc_rate()
91 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()
154 ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info, in ingenic_pll_calc() argument
158 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_calc()
182 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_round_rate() local
184 return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL); in ingenic_pll_round_rate()
206 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_set_rate() local
207 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_set_rate()
213 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate, in ingenic_pll_set_rate()
217 clk_info->name, req_rate, rate); in ingenic_pll_set_rate()
251 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_enable() local
252 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_enable()
285 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_disable() local
286 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_disable()
306 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_pll_is_enabled() local
307 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll; in ingenic_pll_is_enabled()
335 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_get_parent() local
340 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_get_parent()
341 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_get_parent()
342 hw_idx = (reg >> clk_info->mux.shift) & in ingenic_clk_get_parent()
343 GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_get_parent()
350 if (clk_info->parents[i] != -1) in ingenic_clk_get_parent()
361 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_set_parent() local
367 if (clk_info->type & CGU_CLK_MUX) { in ingenic_clk_set_parent()
375 num_poss = 1 << clk_info->mux.bits; in ingenic_clk_set_parent()
377 if (clk_info->parents[hw_idx] == -1) in ingenic_clk_set_parent()
387 mask = GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_set_parent()
388 mask <<= clk_info->mux.shift; in ingenic_clk_set_parent()
393 reg = readl(cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
395 reg |= hw_idx << clk_info->mux.shift; in ingenic_clk_set_parent()
396 writel(reg, cgu->base + clk_info->mux.reg); in ingenic_clk_set_parent()
409 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_recalc_rate() local
415 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
418 if (!(clk_info->div.bypass_mask & BIT(parent))) { in ingenic_clk_recalc_rate()
419 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
420 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
421 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
423 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
424 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
426 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
430 } else if (clk_info->type & CGU_CLK_FIXDIV) { in ingenic_clk_recalc_rate()
431 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
438 ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info, in ingenic_clk_calc_hw_div() argument
443 for (i = 0; i < (1 << clk_info->div.bits) in ingenic_clk_calc_hw_div()
444 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
445 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
446 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
447 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
460 const struct ingenic_cgu_clk_info *clk_info, in ingenic_clk_calc_div() argument
467 if (clk_info->div.bypass_mask & BIT(parent)) in ingenic_clk_calc_div()
473 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
474 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_calc_div()
476 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
480 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
481 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
488 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
489 div *= clk_info->div.div; in ingenic_clk_calc_div()
499 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_round_rate() local
502 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
503 div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate); in ingenic_clk_round_rate()
504 else if (clk_info->type & CGU_CLK_FIXDIV) in ingenic_clk_round_rate()
505 div = clk_info->fixdiv.div; in ingenic_clk_round_rate()
513 const struct ingenic_cgu_clk_info *clk_info) in ingenic_clk_check_stable() argument
517 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg, in ingenic_clk_check_stable()
518 !(reg & BIT(clk_info->div.busy_bit)), in ingenic_clk_check_stable()
527 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_set_rate() local
534 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
535 div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate); in ingenic_clk_set_rate()
541 if (clk_info->div.div_table) in ingenic_clk_set_rate()
542 hw_div = ingenic_clk_calc_hw_div(clk_info, div); in ingenic_clk_set_rate()
544 hw_div = ((div / clk_info->div.div) - 1); in ingenic_clk_set_rate()
547 reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
550 mask = GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_set_rate()
551 reg &= ~(mask << clk_info->div.shift); in ingenic_clk_set_rate()
552 reg |= hw_div << clk_info->div.shift; in ingenic_clk_set_rate()
555 if (clk_info->div.stop_bit != -1) in ingenic_clk_set_rate()
556 reg &= ~BIT(clk_info->div.stop_bit); in ingenic_clk_set_rate()
559 if (clk_info->div.ce_bit != -1) in ingenic_clk_set_rate()
560 reg |= BIT(clk_info->div.ce_bit); in ingenic_clk_set_rate()
563 writel(reg, cgu->base + clk_info->div.reg); in ingenic_clk_set_rate()
566 if (clk_info->div.busy_bit != -1) in ingenic_clk_set_rate()
567 ret = ingenic_clk_check_stable(cgu, clk_info); in ingenic_clk_set_rate()
579 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_enable() local
583 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_enable()
586 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); in ingenic_clk_enable()
589 if (clk_info->gate.delay_us) in ingenic_clk_enable()
590 udelay(clk_info->gate.delay_us); in ingenic_clk_enable()
599 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_disable() local
603 if (clk_info->type & CGU_CLK_GATE) { in ingenic_clk_disable()
606 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); in ingenic_clk_disable()
614 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk); in ingenic_clk_is_enabled() local
618 if (clk_info->type & CGU_CLK_GATE) in ingenic_clk_is_enabled()
619 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); in ingenic_clk_is_enabled()
643 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx]; in ingenic_register_clock() local
651 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names)); in ingenic_register_clock()
653 if (clk_info->type == CGU_CLK_EXT) { in ingenic_register_clock()
654 clk = of_clk_get_by_name(cgu->np, clk_info->name); in ingenic_register_clock()
657 __func__, clk_info->name); in ingenic_register_clock()
661 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()
670 if (!clk_info->type) { in ingenic_register_clock()
672 clk_info->name); in ingenic_register_clock()
686 clk_init.name = clk_info->name; in ingenic_register_clock()
687 clk_init.flags = clk_info->flags; in ingenic_register_clock()
690 caps = clk_info->type; in ingenic_register_clock()
703 num_possible = 1 << clk_info->mux.bits; in ingenic_register_clock()
705 num_possible = ARRAY_SIZE(clk_info->parents); in ingenic_register_clock()
708 if (clk_info->parents[i] == -1) in ingenic_register_clock()
711 parent = cgu->clocks.clks[clk_info->parents[i]]; in ingenic_register_clock()
720 BUG_ON(clk_info->parents[0] == -1); in ingenic_register_clock()
722 parent = cgu->clocks.clks[clk_info->parents[0]]; in ingenic_register_clock()
727 clk_init.ops = clk_info->custom.clk_ops; in ingenic_register_clock()
768 clk_info->name); in ingenic_register_clock()
773 err = clk_register_clkdev(clk, clk_info->name, NULL); in ingenic_register_clock()