Lines Matching refs:clk_lock
52 static DEFINE_SPINLOCK(clk_lock);
186 ARRAY_SIZE(uart_factor_tbl), &clk_lock); in mmp2_clk_init()
191 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in mmp2_clk_init()
195 apbc_base + APBC_TWSI1, 10, 0, &clk_lock); in mmp2_clk_init()
199 apbc_base + APBC_TWSI2, 10, 0, &clk_lock); in mmp2_clk_init()
203 apbc_base + APBC_TWSI3, 10, 0, &clk_lock); in mmp2_clk_init()
207 apbc_base + APBC_TWSI4, 10, 0, &clk_lock); in mmp2_clk_init()
211 apbc_base + APBC_TWSI5, 10, 0, &clk_lock); in mmp2_clk_init()
215 apbc_base + APBC_GPIO, 10, 0, &clk_lock); in mmp2_clk_init()
219 apbc_base + APBC_KPC, 10, 0, &clk_lock); in mmp2_clk_init()
223 apbc_base + APBC_RTC, 10, 0, &clk_lock); in mmp2_clk_init()
227 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in mmp2_clk_init()
231 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in mmp2_clk_init()
235 apbc_base + APBC_PWM2, 10, 0, &clk_lock); in mmp2_clk_init()
239 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in mmp2_clk_init()
245 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in mmp2_clk_init()
250 apbc_base + APBC_UART0, 10, 0, &clk_lock); in mmp2_clk_init()
256 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in mmp2_clk_init()
261 apbc_base + APBC_UART1, 10, 0, &clk_lock); in mmp2_clk_init()
267 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); in mmp2_clk_init()
272 apbc_base + APBC_UART2, 10, 0, &clk_lock); in mmp2_clk_init()
278 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); in mmp2_clk_init()
283 apbc_base + APBC_UART3, 10, 0, &clk_lock); in mmp2_clk_init()
289 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in mmp2_clk_init()
293 apbc_base + APBC_SSP0, 10, 0, &clk_lock); in mmp2_clk_init()
299 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in mmp2_clk_init()
303 apbc_base + APBC_SSP1, 10, 0, &clk_lock); in mmp2_clk_init()
309 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); in mmp2_clk_init()
313 apbc_base + APBC_SSP2, 10, 0, &clk_lock); in mmp2_clk_init()
319 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); in mmp2_clk_init()
323 apbc_base + APBC_SSP3, 10, 0, &clk_lock); in mmp2_clk_init()
329 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); in mmp2_clk_init()
334 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
338 0x1b, &clk_lock); in mmp2_clk_init()
342 0x1b, &clk_lock); in mmp2_clk_init()
346 0x1b, &clk_lock); in mmp2_clk_init()
350 0x1b, &clk_lock); in mmp2_clk_init()
354 0x9, &clk_lock); in mmp2_clk_init()
360 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); in mmp2_clk_init()
365 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
369 apmu_base + APMU_DISP0, 0x1b, &clk_lock); in mmp2_clk_init()
373 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock); in mmp2_clk_init()
377 apmu_base + APMU_DISP0, 0x1024, &clk_lock); in mmp2_clk_init()
383 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); in mmp2_clk_init()
388 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
392 apmu_base + APMU_DISP1, 0x1b, &clk_lock); in mmp2_clk_init()
396 apmu_base + APMU_CCIC0, 0x1800, &clk_lock); in mmp2_clk_init()
402 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); in mmp2_clk_init()
407 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
411 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in mmp2_clk_init()
415 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in mmp2_clk_init()
420 10, 5, 0, &clk_lock); in mmp2_clk_init()
424 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in mmp2_clk_init()
430 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); in mmp2_clk_init()
435 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock); in mmp2_clk_init()
439 apmu_base + APMU_CCIC1, 0x1b, &clk_lock); in mmp2_clk_init()
443 apmu_base + APMU_CCIC1, 0x24, &clk_lock); in mmp2_clk_init()
448 10, 5, 0, &clk_lock); in mmp2_clk_init()
452 apmu_base + APMU_CCIC1, 0x300, &clk_lock); in mmp2_clk_init()