Lines Matching refs:clk_lock
45 static DEFINE_SPINLOCK(clk_lock);
157 ARRAY_SIZE(uart_factor_tbl), &clk_lock); in pxa168_clk_init()
162 apbc_base + APBC_TWSI0, 10, 0, &clk_lock); in pxa168_clk_init()
166 apbc_base + APBC_TWSI1, 10, 0, &clk_lock); in pxa168_clk_init()
170 apbc_base + APBC_GPIO, 10, 0, &clk_lock); in pxa168_clk_init()
174 apbc_base + APBC_KPC, 10, 0, &clk_lock); in pxa168_clk_init()
178 apbc_base + APBC_RTC, 10, 0, &clk_lock); in pxa168_clk_init()
182 apbc_base + APBC_PWM0, 10, 0, &clk_lock); in pxa168_clk_init()
186 apbc_base + APBC_PWM1, 10, 0, &clk_lock); in pxa168_clk_init()
190 apbc_base + APBC_PWM2, 10, 0, &clk_lock); in pxa168_clk_init()
194 apbc_base + APBC_PWM3, 10, 0, &clk_lock); in pxa168_clk_init()
200 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
205 apbc_base + APBC_UART0, 10, 0, &clk_lock); in pxa168_clk_init()
211 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
216 apbc_base + APBC_UART1, 10, 0, &clk_lock); in pxa168_clk_init()
222 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
227 apbc_base + APBC_UART2, 10, 0, &clk_lock); in pxa168_clk_init()
233 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); in pxa168_clk_init()
237 10, 0, &clk_lock); in pxa168_clk_init()
243 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); in pxa168_clk_init()
247 10, 0, &clk_lock); in pxa168_clk_init()
253 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); in pxa168_clk_init()
257 10, 0, &clk_lock); in pxa168_clk_init()
263 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); in pxa168_clk_init()
267 10, 0, &clk_lock); in pxa168_clk_init()
273 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); in pxa168_clk_init()
277 10, 0, &clk_lock); in pxa168_clk_init()
281 0x19b, &clk_lock); in pxa168_clk_init()
287 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
291 0x1b, &clk_lock); in pxa168_clk_init()
297 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); in pxa168_clk_init()
301 0x1b, &clk_lock); in pxa168_clk_init()
305 0x9, &clk_lock); in pxa168_clk_init()
309 0x12, &clk_lock); in pxa168_clk_init()
315 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
319 apmu_base + APMU_DISP0, 0x1b, &clk_lock); in pxa168_clk_init()
323 apmu_base + APMU_DISP0, 0x24, &clk_lock); in pxa168_clk_init()
329 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
333 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in pxa168_clk_init()
339 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); in pxa168_clk_init()
343 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in pxa168_clk_init()
348 10, 5, 0, &clk_lock); in pxa168_clk_init()
352 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in pxa168_clk_init()