Lines Matching refs:soc_desc
58 const struct clk_corediv_soc_desc *soc_desc; member
82 const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; in clk_corediv_is_enabled() local
84 u32 enable_mask = BIT(desc->fieldbit) << soc_desc->enable_bit_offset; in clk_corediv_is_enabled()
92 const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; in clk_corediv_enable() local
100 reg |= (BIT(desc->fieldbit) << soc_desc->enable_bit_offset); in clk_corediv_enable()
111 const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; in clk_corediv_disable() local
119 reg &= ~(BIT(desc->fieldbit) << soc_desc->enable_bit_offset); in clk_corediv_disable()
129 const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; in clk_corediv_recalc_rate() local
133 reg = readl(corediv->reg + soc_desc->ratio_offset); in clk_corediv_recalc_rate()
157 const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc; in clk_corediv_set_rate() local
167 reg = readl(corediv->reg + soc_desc->ratio_offset); in clk_corediv_set_rate()
170 writel(reg, corediv->reg + soc_desc->ratio_offset); in clk_corediv_set_rate()
177 reg = readl(corediv->reg) | soc_desc->ratio_reload; in clk_corediv_set_rate()
185 reg &= ~(CORE_CLK_DIV_RATIO_MASK | soc_desc->ratio_reload); in clk_corediv_set_rate()
252 const struct clk_corediv_soc_desc *soc_desc) in mvebu_corediv_clk_init() argument
268 clk_data.clk_num = soc_desc->ndescs; in mvebu_corediv_clk_init()
289 init.ops = &soc_desc->ops; in mvebu_corediv_clk_init()
292 corediv[i].soc_desc = soc_desc; in mvebu_corediv_clk_init()
293 corediv[i].desc = soc_desc->descs + i; in mvebu_corediv_clk_init()