Lines Matching refs:mult
74 unsigned int mult; in cpg_pll_clk_recalc_rate() local
76 mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; in cpg_pll_clk_recalc_rate()
78 return parent_rate * mult * 2; in cpg_pll_clk_recalc_rate()
84 unsigned int min_mult, max_mult, mult; in cpg_pll_clk_determine_rate() local
93 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
94 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate()
96 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
104 unsigned int mult; in cpg_pll_clk_set_rate() local
107 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2); in cpg_pll_clk_set_rate()
108 mult = clamp(mult, 1U, 256U); in cpg_pll_clk_set_rate()
114 FIELD_PREP(CPG_PLLxCR0_NI, mult - 1)); in cpg_pll_clk_set_rate()
199 unsigned int mult; in cpg_z_clk_recalc_rate() local
203 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
205 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, in cpg_z_clk_recalc_rate()
213 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
233 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate()
234 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
236 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
244 unsigned int mult; in cpg_z_clk_set_rate() local
247 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, in cpg_z_clk_set_rate()
249 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
254 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); in cpg_z_clk_set_rate()
337 unsigned int mult = 1; in rcar_gen4_cpg_clk_register() local
351 mult = cpg_pll_config->pll1_mult; in rcar_gen4_cpg_clk_register()
365 mult = cpg_pll_config->pll2_mult; in rcar_gen4_cpg_clk_register()
370 mult = cpg_pll_config->pll3_mult; in rcar_gen4_cpg_clk_register()
375 mult = cpg_pll_config->pll4_mult; in rcar_gen4_cpg_clk_register()
380 mult = cpg_pll_config->pll5_mult; in rcar_gen4_cpg_clk_register()
385 mult = cpg_pll_config->pll6_mult; in rcar_gen4_cpg_clk_register()
391 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen4_cpg_clk_register()
423 mult = 1; in rcar_gen4_cpg_clk_register()
453 __clk_get_name(parent), 0, mult, div); in rcar_gen4_cpg_clk_register()