Lines Matching refs:hwdata
193 struct sd_hw_data *hwdata = to_sd_hw_data(hw); in rzg2l_cpg_sd_clk_mux_set_parent() local
194 struct rzg2l_cpg_priv *priv = hwdata->priv; in rzg2l_cpg_sd_clk_mux_set_parent()
195 u32 off = GET_REG_OFFSET(hwdata->conf); in rzg2l_cpg_sd_clk_mux_set_parent()
196 u32 shift = GET_SHIFT(hwdata->conf); in rzg2l_cpg_sd_clk_mux_set_parent()
211 bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16; in rzg2l_cpg_sd_clk_mux_set_parent()
236 struct sd_hw_data *hwdata = to_sd_hw_data(hw); in rzg2l_cpg_sd_clk_mux_get_parent() local
237 struct rzg2l_cpg_priv *priv = hwdata->priv; in rzg2l_cpg_sd_clk_mux_get_parent()
238 u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf)); in rzg2l_cpg_sd_clk_mux_get_parent()
240 val >>= GET_SHIFT(hwdata->conf); in rzg2l_cpg_sd_clk_mux_get_parent()
241 val &= GENMASK(GET_WIDTH(hwdata->conf) - 1, 0); in rzg2l_cpg_sd_clk_mux_get_parent()
445 struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw); in rzg2l_cpg_pll5_4_clk_mux_determine_rate() local
446 struct rzg2l_cpg_priv *priv = hwdata->priv; in rzg2l_cpg_pll5_4_clk_mux_determine_rate()
457 struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw); in rzg2l_cpg_pll5_4_clk_mux_set_parent() local
458 struct rzg2l_cpg_priv *priv = hwdata->priv; in rzg2l_cpg_pll5_4_clk_mux_set_parent()
478 struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw); in rzg2l_cpg_pll5_4_clk_mux_get_parent() local
479 struct rzg2l_cpg_priv *priv = hwdata->priv; in rzg2l_cpg_pll5_4_clk_mux_get_parent()
481 return readl(priv->base + GET_REG_OFFSET(hwdata->conf)); in rzg2l_cpg_pll5_4_clk_mux_get_parent()