Lines Matching refs:MHZ
691 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
693 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
700 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
701 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
702 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
703 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
704 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
705 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
706 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
707 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
714 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
715 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
716 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
717 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
718 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
722 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
723 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
724 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
725 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1),
726 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1),
727 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1),
728 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2),
729 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2),
809 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5250_clk_init()
814 if (clk_hw_get_rate(hws[CLK_MOUT_VPLLSRC]) == 24 * MHZ) in exynos5250_clk_init()