Lines Matching refs:clock_data
260 return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id); in clk_stm32_mux_get_parent()
270 stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index); in clk_stm32_mux_set_parent()
289 stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable); in clk_stm32_gate_endisable()
310 return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id); in clk_stm32_gate_is_enabled()
320 stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id); in clk_stm32_gate_disable_unused()
344 ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate); in clk_stm32_divider_set_rate()
360 divider = &div->clock_data->dividers[div->div_id]; in clk_stm32_divider_round_rate()
387 return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate); in clk_stm32_divider_recalc_rate()
408 ret = stm32_divider_set_rate(composite->base, composite->clock_data, in clk_stm32_composite_set_rate()
424 return stm32_divider_get_rate(composite->base, composite->clock_data, in clk_stm32_composite_recalc_rate()
438 divider = &composite->clock_data->dividers[composite->div_id]; in clk_stm32_composite_round_rate()
461 return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id); in clk_stm32_composite_get_parent()
471 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index); in clk_stm32_composite_set_parent()
475 if (composite->clock_data->is_multi_mux) { in clk_stm32_composite_set_parent()
476 struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw); in clk_stm32_composite_set_parent()
495 return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id); in clk_stm32_composite_is_enabled()
503 const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id]; in clk_stm32_has_safe_mux()
515 if (composite->clock_data->is_multi_mux) { in clk_stm32_set_safe_position_mux()
518 other_mux_hw = composite->clock_data->is_multi_mux(hw); in clk_stm32_set_safe_position_mux()
526 stm32_mux_set_parent(composite->base, composite->clock_data, in clk_stm32_set_safe_position_mux()
541 stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel); in clk_stm32_safe_restore_position_mux()
553 stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable); in clk_stm32_composite_gate_endisable()
596 stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id); in clk_stm32_composite_disable_unused()
625 mux->clock_data = data->clock_data; in clk_stm32_mux_register()
646 gate->clock_data = data->clock_data; in clk_stm32_gate_register()
667 div->clock_data = data->clock_data; in clk_stm32_div_register()
688 composite->clock_data = data->clock_data; in clk_stm32_composite_register()