Lines Matching refs:_name
87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
96 .hw.init = CLK_HW_INIT(_name, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \ argument
119 .hw.init = CLK_HW_INIT_HW(_name, \
127 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \ argument
139 .hw.init = CLK_HW_INIT_PARENTS(_name, \
146 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
149 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
155 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
158 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
165 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
173 .hw.init = CLK_HW_INIT(_name, \
180 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
182 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
185 #define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
195 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
202 #define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ argument
206 SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
211 #define SUNXI_CCU_M_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
220 .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
227 #define SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \ argument
235 .hw.init = CLK_HW_INIT_HWS(_name, \
242 #define SUNXI_CCU_M_HWS(_struct, _name, _parent, _reg, _mshift, \ argument
244 SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \