Lines Matching refs:sdmmc_mux
43 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_get_parent() local
50 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_get_parent()
69 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_set_parent() local
73 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_set_parent()
82 writel(val, sdmmc_mux->reg); in clk_sdmmc_mux_set_parent()
90 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_recalc_rate() local
95 val = readl_relaxed(sdmmc_mux->reg); in clk_sdmmc_mux_recalc_rate()
110 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_determine_rate() local
120 div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags); in clk_sdmmc_mux_determine_rate()
124 if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP) in clk_sdmmc_mux_determine_rate()
136 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_set_rate() local
142 div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags); in clk_sdmmc_mux_set_rate()
146 if (sdmmc_mux->lock) in clk_sdmmc_mux_set_rate()
147 spin_lock_irqsave(sdmmc_mux->lock, flags); in clk_sdmmc_mux_set_rate()
157 writel(val, sdmmc_mux->reg); in clk_sdmmc_mux_set_rate()
158 fence_udelay(2, sdmmc_mux->reg); in clk_sdmmc_mux_set_rate()
160 if (sdmmc_mux->lock) in clk_sdmmc_mux_set_rate()
161 spin_unlock_irqrestore(sdmmc_mux->lock, flags); in clk_sdmmc_mux_set_rate()
168 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_is_enabled() local
169 const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; in clk_sdmmc_mux_is_enabled()
170 struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; in clk_sdmmc_mux_is_enabled()
179 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_enable() local
180 const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; in clk_sdmmc_mux_enable()
181 struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; in clk_sdmmc_mux_enable()
190 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_disable() local
191 const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; in clk_sdmmc_mux_disable()
192 struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; in clk_sdmmc_mux_disable()
199 struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); in clk_sdmmc_mux_disable_unused() local
200 const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; in clk_sdmmc_mux_disable_unused()
201 struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; in clk_sdmmc_mux_disable_unused()
241 struct tegra_sdmmc_mux *sdmmc_mux; in tegra_clk_register_sdmmc_mux_div() local
253 sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL); in tegra_clk_register_sdmmc_mux_div()
254 if (!sdmmc_mux) in tegra_clk_register_sdmmc_mux_div()
258 sdmmc_mux->hw.init = &init; in tegra_clk_register_sdmmc_mux_div()
259 sdmmc_mux->reg = clk_base + offset; in tegra_clk_register_sdmmc_mux_div()
260 sdmmc_mux->lock = lock; in tegra_clk_register_sdmmc_mux_div()
261 sdmmc_mux->gate.clk_base = clk_base; in tegra_clk_register_sdmmc_mux_div()
262 sdmmc_mux->gate.regs = bank; in tegra_clk_register_sdmmc_mux_div()
263 sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt; in tegra_clk_register_sdmmc_mux_div()
264 sdmmc_mux->gate.clk_num = clk_num; in tegra_clk_register_sdmmc_mux_div()
265 sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB; in tegra_clk_register_sdmmc_mux_div()
266 sdmmc_mux->div_flags = div_flags; in tegra_clk_register_sdmmc_mux_div()
267 sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops; in tegra_clk_register_sdmmc_mux_div()
269 clk = clk_register(NULL, &sdmmc_mux->hw); in tegra_clk_register_sdmmc_mux_div()
271 kfree(sdmmc_mux); in tegra_clk_register_sdmmc_mux_div()
275 sdmmc_mux->gate.hw.clk = clk; in tegra_clk_register_sdmmc_mux_div()