Lines Matching refs:clk_base
119 static void __iomem *clk_base; variable
1024 static __init void tegra124_periph_clk_init(void __iomem *clk_base, in tegra124_periph_clk_init() argument
1035 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, in tegra124_periph_clk_init()
1040 clk_base + PLLD_MISC, 30, 0, &pll_d_lock); in tegra124_periph_clk_init()
1044 clk_base, 0, 48, in tegra124_periph_clk_init()
1049 clk_base, 0, 82, in tegra124_periph_clk_init()
1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()
1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1079 clk = tegra_clk_register_periph_data(clk_base, init); in tegra124_periph_clk_init()
1083 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params); in tegra124_periph_clk_init()
1086 static void __init tegra124_pll_init(void __iomem *clk_base, in tegra124_pll_init() argument
1092 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, in tegra124_pll_init()
1099 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
1102 clk_base + PLLC_OUT, 1, 0, in tegra124_pll_init()
1114 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra124_pll_init()
1120 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra124_pll_init()
1126 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, in tegra124_pll_init()
1133 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra124_pll_init()
1136 clk_base + PLLM_OUT, 1, 0, in tegra124_pll_init()
1148 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra124_pll_init()
1155 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra124_pll_init()
1179 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra124_pll_init()
1191 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, in tegra124_pll_init()
1197 clk_base + PLLRE_BASE, 16, 4, 0, in tegra124_pll_init()
1204 clk_base, 0, &pll_e_params, NULL); in tegra124_pll_init()
1209 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0, in tegra124_pll_init()
1215 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0, in tegra124_pll_init()
1221 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0, in tegra124_pll_init()
1240 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); in tegra124_wait_cpu_in_reset()
1255 readl(clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_suspend()
1256 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_suspend()
1259 readl(clk_base + CCLKG_BURST_POLICY); in tegra124_cpu_clock_suspend()
1261 readl(clk_base + CCLKG_BURST_POLICY + 4); in tegra124_cpu_clock_suspend()
1267 clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_resume()
1270 clk_base + CCLKG_BURST_POLICY); in tegra124_cpu_clock_resume()
1272 clk_base + CCLKG_BURST_POLICY + 4); in tegra124_cpu_clock_resume()
1380 readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra124_car_barrier()
1392 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra124_clock_assert_dfll_dvco_reset()
1394 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra124_clock_assert_dfll_dvco_reset()
1408 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra124_clock_deassert_dfll_dvco_reset()
1410 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra124_clock_deassert_dfll_dvco_reset()
1461 clk_base = of_iomap(np, 0); in tegra124_132_clock_init_pre()
1462 if (!clk_base) { in tegra124_132_clock_init_pre()
1482 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, in tegra124_132_clock_init_pre()
1487 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq, in tegra124_132_clock_init_pre()
1493 tegra124_pll_init(clk_base, pmc_base); in tegra124_132_clock_init_pre()
1494 tegra124_periph_clk_init(clk_base, pmc_base); in tegra124_132_clock_init_pre()
1495 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, in tegra124_132_clock_init_pre()
1500 plld_base = readl(clk_base + PLLD_BASE); in tegra124_132_clock_init_pre()
1502 writel(plld_base, clk_base + PLLD_BASE); in tegra124_132_clock_init_pre()
1537 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks, in tegra124_132_clock_init_post()
1543 clks[TEGRA124_CLK_EMC] = tegra124_clk_register_emc(clk_base, np, in tegra124_132_clock_init_post()