Lines Matching refs:dt_id
421 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
422 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
423 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
424 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
425 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
426 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
427 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
428 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
429 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
430 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
431 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
432 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
433 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
434 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
435 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
436 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
437 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
438 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
439 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
440 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
441 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
442 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
443 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
444 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
445 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
446 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
447 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
448 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
449 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
450 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
451 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
452 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
453 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
454 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
455 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
456 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
457 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
458 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
459 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
460 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
461 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
462 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
463 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
464 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
465 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
466 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
467 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
468 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
469 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
470 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
471 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
472 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
473 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
474 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
475 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
476 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
477 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
478 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
479 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
480 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
481 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
482 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
483 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
484 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
485 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
486 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
487 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
488 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
489 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
490 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
491 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
492 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
493 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
494 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
495 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
496 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
497 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
498 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
499 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
500 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
501 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
502 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
503 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
504 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
505 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
506 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
507 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
508 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
509 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
510 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
511 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
512 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
513 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
514 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
518 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },
519 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true },
520 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
521 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
522 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
523 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
524 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
525 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
526 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
527 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
528 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
529 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
530 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
531 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
532 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
533 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
534 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
535 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
536 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
537 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
538 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
539 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
540 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
541 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
542 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
543 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
544 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
545 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
546 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
547 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
548 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
549 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
550 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
551 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
552 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
553 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
554 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
555 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
556 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
557 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
558 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
559 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
560 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
561 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
562 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
563 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
564 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
565 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
566 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
567 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
568 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
569 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
570 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },