Lines Matching refs:clk_base
298 static void __iomem *clk_base; variable
504 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_is_enabled()
520 value = readl_relaxed(clk_base + PLLE_MISC0); in tegra210_plle_hw_sequence_start()
525 writel_relaxed(value, clk_base + PLLE_MISC0); in tegra210_plle_hw_sequence_start()
527 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
530 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
532 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
535 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
537 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
547 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
552 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
560 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
562 writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_sequence_start()
570 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
574 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_control_enable()
582 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
584 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_sata_pll_hw_sequence_start()
592 val = readl_relaxed(clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
604 writel_relaxed(val, clk_base + SATA_PLL_CFG0); in tegra210_set_sata_pll_seq_sw()
613 writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset); in tegra210_clk_emc_dll_enable()
619 writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL); in tegra210_clk_emc_dll_update_setting()
625 writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC); in tegra210_clk_emc_update_setting()
633 val = readl_relaxed(clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
634 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
635 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
636 writel_relaxed(val, clk_base + mbist->lvl2_offset); in tegra210_generic_mbist_war()
637 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
647 csi_src = readl_relaxed(clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
648 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
649 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
651 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
652 writel_relaxed(ovra | BIT(15), clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
653 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
654 writel_relaxed(ovre | BIT(3), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
655 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
657 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); in tegra210_venc_mbist_war()
658 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_venc_mbist_war()
659 writel_relaxed(csi_src, clk_base + PLLD_BASE); in tegra210_venc_mbist_war()
660 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
669 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
670 writel_relaxed(ovra | BIT(1), clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
671 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
679 writel_relaxed(ovra, clk_base + LVL2_CLK_GATE_OVRA); in tegra210_disp_mbist_war()
680 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
687 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
688 writel_relaxed(ovre | BIT(5), clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
689 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
699 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_vic_mbist_war()
700 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
709 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
710 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
711 writel_relaxed(ovrc | BIT(1), clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
713 clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
714 fence_udelay(1, clk_base); in tegra210_ape_mbist_war()
733 writel_relaxed(ovrc, clk_base + LVL2_CLK_GATE_OVRC); in tegra210_ape_mbist_war()
734 writel_relaxed(ovre, clk_base + LVL2_CLK_GATE_OVRE); in tegra210_ape_mbist_war()
735 fence_udelay(1, clk_base); in tegra210_ape_mbist_war()
764 _pll_misc_chk_default(clk_base, params, 0, default_val, in pllcx_check_defaults()
768 _pll_misc_chk_default(clk_base, params, 1, default_val, in pllcx_check_defaults()
772 _pll_misc_chk_default(clk_base, params, 2, default_val, in pllcx_check_defaults()
776 _pll_misc_chk_default(clk_base, params, 3, default_val, in pllcx_check_defaults()
785 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()
796 clk_base + pllcx->params->ext_misc_reg[0]); in tegra210_pllcx_set_defaults()
798 clk_base + pllcx->params->ext_misc_reg[1]); in tegra210_pllcx_set_defaults()
800 clk_base + pllcx->params->ext_misc_reg[2]); in tegra210_pllcx_set_defaults()
802 clk_base + pllcx->params->ext_misc_reg[3]); in tegra210_pllcx_set_defaults()
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
852 _pll_misc_chk_default(clk_base, plla->params, 0, val, in tegra210_plla_set_defaults()
856 _pll_misc_chk_default(clk_base, plla->params, 2, val, in tegra210_plla_set_defaults()
860 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
863 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
871 writel_relaxed(val, clk_base + plla->params->base_reg); in tegra210_plla_set_defaults()
873 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
875 clk_base + plla->params->ext_misc_reg[2]); in tegra210_plla_set_defaults()
890 if (readl_relaxed(clk_base + plld->params->base_reg) & in tegra210_plld_set_defaults()
898 _pll_misc_chk_default(clk_base, plld->params, 1, in tegra210_plld_set_defaults()
905 _pll_misc_chk_default(clk_base, plld->params, 0, val, in tegra210_plld_set_defaults()
913 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
916 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
922 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
926 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
927 writel_relaxed(PLLD_MISC1_DEFAULT_VALUE, clk_base + in tegra210_plld_set_defaults()
940 u32 val = readl_relaxed(clk_base + plldss->params->base_reg); in plldss_defaults()
957 _pll_misc_chk_default(clk_base, plldss->params, 0, default_val, in plldss_defaults()
968 _pll_misc_chk_default(clk_base, plldss->params, 1, in plldss_defaults()
971 _pll_misc_chk_default(clk_base, plldss->params, 2, in plldss_defaults()
974 _pll_misc_chk_default(clk_base, plldss->params, 3, in plldss_defaults()
978 _pll_misc_chk_default(clk_base, plldss->params, 1, in plldss_defaults()
990 writel_relaxed(val, clk_base + in plldss_defaults()
994 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
997 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
1006 writel_relaxed(val, clk_base + plldss->params->base_reg); in plldss_defaults()
1010 writel_relaxed(misc0_val, clk_base + in plldss_defaults()
1016 writel_relaxed(misc0_val, clk_base + in plldss_defaults()
1020 clk_base + plldss->params->ext_misc_reg[1]); in plldss_defaults()
1021 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); in plldss_defaults()
1022 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); in plldss_defaults()
1059 u32 val = readl_relaxed(clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1080 _pll_misc_chk_default(clk_base, pllre->params, 0, val, in tegra210_pllre_set_defaults()
1084 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1091 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1103 writel_relaxed(val, clk_base + pllre->params->base_reg); in tegra210_pllre_set_defaults()
1105 clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1149 _pll_misc_chk_default(clk_base, pll->params, 0, default_val, in pllx_check_defaults()
1153 _pll_misc_chk_default(clk_base, pll->params, 1, default_val, in pllx_check_defaults()
1158 _pll_misc_chk_default(clk_base, pll->params, 2, in pllx_check_defaults()
1162 _pll_misc_chk_default(clk_base, pll->params, 3, default_val, in pllx_check_defaults()
1166 _pll_misc_chk_default(clk_base, pll->params, 4, default_val, in pllx_check_defaults()
1170 _pll_misc_chk_default(clk_base, pll->params, 5, default_val, in pllx_check_defaults()
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1199 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1202 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1205 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1212 writel_relaxed(PLLX_MISC0_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1216 writel_relaxed(PLLX_MISC1_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1220 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1223 writel_relaxed(PLLX_MISC3_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1227 writel_relaxed(PLLX_MISC4_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1229 writel_relaxed(PLLX_MISC5_DEFAULT_VALUE, clk_base + in tegra210_pllx_set_defaults()
1237 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg); in tegra210_pllmb_set_defaults()
1249 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, in tegra210_pllmb_set_defaults()
1255 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1258 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1266 clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1285 _pll_misc_chk_default(clk_base, pll->params, 0, val, in pllp_check_defaults()
1291 _pll_misc_chk_default(clk_base, pll->params, 1, val, in pllp_check_defaults()
1298 u32 val = readl_relaxed(clk_base + pllp->params->base_reg); in tegra210_pllp_set_defaults()
1313 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1317 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1325 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1328 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1332 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1350 _pll_misc_chk_default(clk_base, params, 0, val, in pllu_check_defaults()
1355 _pll_misc_chk_default(clk_base, params, 1, val, in pllu_check_defaults()
1361 u32 val = readl_relaxed(clk_base + pllu->base_reg); in tegra210_pllu_set_defaults()
1376 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1379 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1381 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1384 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1392 clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1394 clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1421 val = readl_relaxed(clk_base + reg); in tegra210_wait_for_mask()
1438 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1441 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1444 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1446 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1452 base = readl_relaxed(clk_base + pllx->params->base_reg) & in tegra210_pllx_dyn_ramp()
1455 writel_relaxed(base, clk_base + pllx->params->base_reg); in tegra210_pllx_dyn_ramp()
1459 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
2779 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2787 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_in_iddq()
2795 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2797 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_put_utmipll_out_iddq()
2817 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2819 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2823 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2833 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2836 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2847 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2850 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2853 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2858 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2865 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra210_utmi_param_configure()
2868 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2871 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra210_utmi_param_configure()
2873 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2876 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2880 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); in tegra210_utmi_param_configure()
2882 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); in tegra210_utmi_param_configure()
2887 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2889 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_utmi_param_configure()
2911 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2913 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2914 fence_udelay(5, clk_base); in tegra210_enable_pllu()
2916 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2921 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2922 fence_udelay(1, clk_base); in tegra210_enable_pllu()
2924 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2948 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2958 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2960 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2962 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2968 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2970 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0); in tegra210_init_pllu()
2972 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0); in tegra210_init_pllu()
2973 fence_udelay(1, clk_base); in tegra210_init_pllu()
2975 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2977 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0); in tegra210_init_pllu()
2978 fence_udelay(1, clk_base); in tegra210_init_pllu()
2980 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2982 writel_relaxed(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2986 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra210_init_pllu()
3041 clk_base + CLK_SOURCE_EMC, in tegra210_clk_register_mc()
3090 void __iomem *clk_base, in tegra210_periph_clk_init() argument
3101 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, in tegra210_periph_clk_init()
3105 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()
3109 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, in tegra210_periph_clk_init()
3115 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); in tegra210_periph_clk_init()
3120 clk_base, 0, 48, in tegra210_periph_clk_init()
3126 clk_base, 0, 82, in tegra210_periph_clk_init()
3132 CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, in tegra210_periph_clk_init()
3139 ARRAY_SIZE(la_parents), &tegra210_la, clk_base, in tegra210_periph_clk_init()
3144 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3150 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3156 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0, in tegra210_periph_clk_init()
3160 clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base, in tegra210_periph_clk_init()
3165 clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base, in tegra210_periph_clk_init()
3180 clk = tegra_clk_register_periph_data(clk_base, init); in tegra210_periph_clk_init()
3184 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); in tegra210_periph_clk_init()
3187 clk = tegra210_clk_register_emc(np, clk_base); in tegra210_periph_clk_init()
3194 static void __init tegra210_pll_init(void __iomem *clk_base, in tegra210_pll_init() argument
3200 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base, in tegra210_pll_init()
3208 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3211 clk_base + PLLC_OUT, 1, 0, in tegra210_pll_init()
3223 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, in tegra210_pll_init()
3229 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, in tegra210_pll_init()
3235 clk = tegra_clk_register_pllm("pll_m", "osc", clk_base, pmc, in tegra210_pll_init()
3241 clk = tegra_clk_register_pllmb("pll_mb", "osc", clk_base, pmc, in tegra210_pll_init()
3273 clk_base + PLLU_BASE, 16, 4, 0, in tegra210_pll_init()
3280 clk_base + PLLU_OUTA, 0, in tegra210_pll_init()
3284 clk_base + PLLU_OUTA, 1, 0, in tegra210_pll_init()
3291 clk_base + PLLU_OUTA, 0, in tegra210_pll_init()
3295 clk_base + PLLU_OUTA, 17, 16, in tegra210_pll_init()
3302 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3309 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3316 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3322 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra210_pll_init()
3335 clk_base, pmc, 0, in tegra210_pll_init()
3342 clk_base + PLLRE_BASE, 16, 5, 0, in tegra210_pll_init()
3348 clk_base + PLLRE_OUT1, 0, in tegra210_pll_init()
3352 clk_base + PLLRE_OUT1, 1, 0, in tegra210_pll_init()
3358 clk_base, 0, &pll_e_params, NULL); in tegra210_pll_init()
3363 clk = tegra_clk_register_pllre("pll_c4_vco", "pll_ref", clk_base, pmc, in tegra210_pll_init()
3370 clk_base + PLLC4_BASE, 19, 4, 0, in tegra210_pll_init()
3389 clk_base + PLLC4_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra210_pll_init()
3392 clk_base + PLLC4_OUT, 1, 0, in tegra210_pll_init()
3398 clk = tegra_clk_register_pllss_tegra210("pll_dp", "pll_ref", clk_base, in tegra210_pll_init()
3404 clk = tegra_clk_register_pllss_tegra210("pll_d2", "pll_ref", clk_base, in tegra210_pll_init()
3429 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); in tegra210_wait_cpu_in_reset()
3440 #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
3442 writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
3457 spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0); in tegra210_clk_suspend()
3458 misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB); in tegra210_clk_suspend()
3459 clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM); in tegra210_clk_suspend()
3472 tegra_clk_osc_resume(clk_base); in tegra210_clk_resume()
3478 writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0); in tegra210_clk_resume()
3479 writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB); in tegra210_clk_resume()
3480 writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM); in tegra210_clk_resume()
3492 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_L, clk_base + CLK_OUT_ENB_L); in tegra210_clk_resume()
3493 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_H, clk_base + CLK_OUT_ENB_H); in tegra210_clk_resume()
3494 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_U, clk_base + CLK_OUT_ENB_U); in tegra210_clk_resume()
3495 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_V, clk_base + CLK_OUT_ENB_V); in tegra210_clk_resume()
3496 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_W, clk_base + CLK_OUT_ENB_W); in tegra210_clk_resume()
3497 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_X, clk_base + CLK_OUT_ENB_X); in tegra210_clk_resume()
3498 writel_relaxed(TEGRA210_CLK_ENB_VLD_MSK_Y, clk_base + CLK_OUT_ENB_Y); in tegra210_clk_resume()
3501 fence_udelay(2, clk_base); in tegra210_clk_resume()
3515 readl(clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_suspend()
3516 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_suspend()
3522 clk_base + CLK_SOURCE_CSITE); in tegra210_cpu_clock_resume()
3626 readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_car_barrier()
3638 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_clock_assert_dfll_dvco_reset()
3640 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra210_clock_assert_dfll_dvco_reset()
3654 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra210_clock_deassert_dfll_dvco_reset()
3656 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra210_clock_deassert_dfll_dvco_reset()
3666 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET); in tegra210_reset_assert()
3678 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); in tegra210_reset_deassert()
3686 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR); in tegra210_reset_deassert()
3738 clk_base = of_iomap(np, 0); in tegra210_clock_init()
3739 if (!clk_base) { in tegra210_clock_init()
3777 clks = tegra_clk_init(clk_base, TEGRA210_CLK_CLK_MAX, in tegra210_clock_init()
3782 value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT; in tegra210_clock_init()
3785 if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq, in tegra210_clock_init()
3791 tegra210_pll_init(clk_base, pmc_base); in tegra210_clock_init()
3792 tegra210_periph_clk_init(np, clk_base, pmc_base); in tegra210_clock_init()
3793 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks, in tegra210_clock_init()
3798 value = readl(clk_base + PLLD_BASE); in tegra210_clock_init()
3800 writel(value, clk_base + PLLD_BASE); in tegra210_clock_init()
3804 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, in tegra210_clock_init()