Lines Matching refs:ext_misc_reg
742 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]); in _pll_misc_chk_default()
796 clk_base + pllcx->params->ext_misc_reg[0]); in tegra210_pllcx_set_defaults()
798 clk_base + pllcx->params->ext_misc_reg[1]); in tegra210_pllcx_set_defaults()
800 clk_base + pllcx->params->ext_misc_reg[2]); in tegra210_pllcx_set_defaults()
802 clk_base + pllcx->params->ext_misc_reg[3]); in tegra210_pllcx_set_defaults()
860 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
863 writel_relaxed(val, clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
873 clk_base + plla->params->ext_misc_reg[0]); in tegra210_plla_set_defaults()
875 clk_base + plla->params->ext_misc_reg[2]); in tegra210_plla_set_defaults()
913 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
916 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
922 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
926 writel_relaxed(val, clk_base + plld->params->ext_misc_reg[0]); in tegra210_plld_set_defaults()
928 plld->params->ext_misc_reg[1]); in tegra210_plld_set_defaults()
976 } else if (plldss->params->ext_misc_reg[1]) { in plldss_defaults()
994 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
997 writel_relaxed(val, clk_base + plldss->params->ext_misc_reg[0]); in plldss_defaults()
1009 if (!plldss->params->ext_misc_reg[1]) { in plldss_defaults()
1011 plldss->params->ext_misc_reg[0]); in plldss_defaults()
1017 plldss->params->ext_misc_reg[0]); in plldss_defaults()
1020 clk_base + plldss->params->ext_misc_reg[1]); in plldss_defaults()
1021 writel_relaxed(misc2_val, clk_base + plldss->params->ext_misc_reg[2]); in plldss_defaults()
1022 writel_relaxed(misc3_val, clk_base + plldss->params->ext_misc_reg[3]); in plldss_defaults()
1084 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1091 writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1105 clk_base + pllre->params->ext_misc_reg[0]); in tegra210_pllre_set_defaults()
1199 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1202 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1205 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1213 pllx->params->ext_misc_reg[0]); in tegra210_pllx_set_defaults()
1217 pllx->params->ext_misc_reg[1]); in tegra210_pllx_set_defaults()
1220 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_set_defaults()
1224 pllx->params->ext_misc_reg[3]); in tegra210_pllx_set_defaults()
1228 pllx->params->ext_misc_reg[4]); in tegra210_pllx_set_defaults()
1230 pllx->params->ext_misc_reg[5]); in tegra210_pllx_set_defaults()
1255 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1258 writel_relaxed(val, clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1266 clk_base + pllmb->params->ext_misc_reg[0]); in tegra210_pllmb_set_defaults()
1313 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1317 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1325 clk_base + pllp->params->ext_misc_reg[0]); in tegra210_pllp_set_defaults()
1328 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1332 writel_relaxed(val, clk_base + pllp->params->ext_misc_reg[1]); in tegra210_pllp_set_defaults()
1376 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1379 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1381 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1384 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1392 clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1394 clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1438 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1441 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1444 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1446 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1449 tegra210_wait_for_mask(pllx, pllx->params->ext_misc_reg[2], in tegra210_pllx_dyn_ramp()
1459 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); in tegra210_pllx_dyn_ramp()
1665 .ext_misc_reg[0] = PLLX_MISC0,
1666 .ext_misc_reg[1] = PLLX_MISC1,
1667 .ext_misc_reg[2] = PLLX_MISC2,
1668 .ext_misc_reg[3] = PLLX_MISC3,
1669 .ext_misc_reg[4] = PLLX_MISC4,
1670 .ext_misc_reg[5] = PLLX_MISC5,
1720 .ext_misc_reg[0] = PLLC_MISC0,
1721 .ext_misc_reg[1] = PLLC_MISC1,
1722 .ext_misc_reg[2] = PLLC_MISC2,
1723 .ext_misc_reg[3] = PLLC_MISC3,
1763 .ext_misc_reg[0] = PLLC2_MISC0,
1764 .ext_misc_reg[1] = PLLC2_MISC1,
1765 .ext_misc_reg[2] = PLLC2_MISC2,
1766 .ext_misc_reg[3] = PLLC2_MISC3,
1793 .ext_misc_reg[0] = PLLC3_MISC0,
1794 .ext_misc_reg[1] = PLLC3_MISC1,
1795 .ext_misc_reg[2] = PLLC3_MISC2,
1796 .ext_misc_reg[3] = PLLC3_MISC3,
1850 .ext_misc_reg[0] = PLLC4_MISC0,
1907 .ext_misc_reg[0] = PLLM_MISC2,
1908 .ext_misc_reg[1] = PLLM_MISC1,
1933 .ext_misc_reg[0] = PLLMB_MISC1,
2013 .ext_misc_reg[0] = PLLRE_MISC0,
2053 .ext_misc_reg[0] = PLLP_MISC0,
2054 .ext_misc_reg[1] = PLLP_MISC1,
2081 .ext_misc_reg[0] = PLLA1_MISC0,
2082 .ext_misc_reg[1] = PLLA1_MISC1,
2083 .ext_misc_reg[2] = PLLA1_MISC2,
2084 .ext_misc_reg[3] = PLLA1_MISC3,
2133 .ext_misc_reg[0] = PLLA_MISC0,
2134 .ext_misc_reg[1] = PLLA_MISC1,
2135 .ext_misc_reg[2] = PLLA_MISC2,
2180 .ext_misc_reg[0] = PLLD_MISC0,
2181 .ext_misc_reg[1] = PLLD_MISC1,
2222 .ext_misc_reg[0] = PLLD2_MISC0,
2223 .ext_misc_reg[1] = PLLD2_MISC1,
2224 .ext_misc_reg[2] = PLLD2_MISC2,
2225 .ext_misc_reg[3] = PLLD2_MISC3,
2265 .ext_misc_reg[0] = PLLDP_MISC,
2266 .ext_misc_reg[1] = PLLDP_SS_CFG,
2267 .ext_misc_reg[2] = PLLDP_SS_CTRL1,
2268 .ext_misc_reg[3] = PLLDP_SS_CTRL2,
2308 .ext_misc_reg[0] = PLLU_MISC0,
2309 .ext_misc_reg[1] = PLLU_MISC1,
2911 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2913 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()