Lines Matching refs:input_rate
1111 unsigned long input_rate; in pllx_get_dyn_steps() local
1115 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in pllx_get_dyn_steps()
1117 input_rate = 38400000; in pllx_get_dyn_steps()
1119 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); in pllx_get_dyn_steps()
1121 switch (input_rate) { in pllx_get_dyn_steps()
1138 __func__, input_rate); in pllx_get_dyn_steps()
1464 cfg->input_rate / cfg->m * cfg->n / in tegra210_pllx_dyn_ramp()
1480 unsigned long rate, unsigned long input_rate) in tegra210_pll_fixed_mdiv_cfg() argument
1501 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); in tegra210_pll_fixed_mdiv_cfg()
1510 cf = input_rate / cfg->m; in tegra210_pll_fixed_mdiv_cfg()
1514 cfg->output_rate = input_rate; in tegra210_pll_fixed_mdiv_cfg()
1532 cfg->input_rate = input_rate; in tegra210_pll_fixed_mdiv_cfg()
2899 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) { in tegra210_enable_pllu()
2900 if (fentry->input_rate == pll_ref_freq) in tegra210_enable_pllu()
2904 if (!fentry->input_rate) { in tegra210_enable_pllu()