Lines Matching refs:clk_base
151 static void __iomem *clk_base; variable
820 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
823 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
829 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
832 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
837 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
847 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, in tegra30_pll_init()
852 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
862 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
875 clk_base + PLLE_AUX, 2, 1, 0, NULL); in tegra30_pll_init()
898 clk_base + SUPER_CCLKG_DIVIDER, 0, in tegra30_super_clk_init()
907 clk_base + SUPER_CCLKG_DIVIDER, 0, in tegra30_super_clk_init()
916 clk_base + SUPER_CCLKG_DIVIDER, 0, in tegra30_super_clk_init()
924 clk_base + CCLKG_BURST_POLICY, in tegra30_super_clk_init()
933 clk_base + SUPER_CCLKLP_DIVIDER, 0, in tegra30_super_clk_init()
942 clk_base + SUPER_CCLKLP_DIVIDER, 0, in tegra30_super_clk_init()
951 clk_base + SUPER_CCLKLP_DIVIDER, 0, in tegra30_super_clk_init()
959 clk_base + CCLKLP_BURST_POLICY, in tegra30_super_clk_init()
969 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL); in tegra30_super_clk_init()
1008 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, in tegra30_periph_clk_init()
1013 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1018 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, in tegra30_periph_clk_init()
1023 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true); in tegra30_periph_clk_init()
1027 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra30_periph_clk_init()
1032 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1037 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1043 clk = tegra_clk_register_periph_data(clk_base, data); in tegra30_periph_clk_init()
1052 clk_base, data->offset); in tegra30_periph_clk_init()
1056 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params); in tegra30_periph_clk_init()
1065 reg = readl(clk_base + in tegra30_wait_cpu_in_reset()
1076 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); in tegra30_put_cpu_in_reset()
1083 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); in tegra30_cpu_out_of_reset()
1090 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); in tegra30_enable_cpu_clock()
1091 readl(clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); in tegra30_enable_cpu_clock()
1098 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra30_disable_cpu_clock()
1100 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); in tegra30_disable_cpu_clock()
1109 cpu_rst_status = readl(clk_base + in tegra30_cpu_rail_off_ready()
1125 readl(clk_base + CLK_RESET_SOURCE_CSITE); in tegra30_cpu_clock_suspend()
1126 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE); in tegra30_cpu_clock_suspend()
1129 readl(clk_base + CLK_RESET_CCLK_BURST); in tegra30_cpu_clock_suspend()
1131 readl(clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_suspend()
1133 readl(clk_base + CLK_RESET_PLLX_MISC); in tegra30_cpu_clock_suspend()
1135 readl(clk_base + CLK_RESET_CCLK_DIVIDER); in tegra30_cpu_clock_suspend()
1144 reg = readl(clk_base + CLK_RESET_CCLK_BURST); in tegra30_cpu_clock_resume()
1155 misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC); in tegra30_cpu_clock_resume()
1156 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_resume()
1162 clk_base + CLK_RESET_PLLX_MISC); in tegra30_cpu_clock_resume()
1164 clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_resume()
1177 clk_base + CLK_RESET_CCLK_DIVIDER); in tegra30_cpu_clock_resume()
1179 clk_base + CLK_RESET_CCLK_BURST); in tegra30_cpu_clock_resume()
1182 clk_base + CLK_RESET_SOURCE_CSITE); in tegra30_cpu_clock_resume()
1311 clk_base = of_iomap(np, 0); in tegra30_clock_init()
1312 if (!clk_base) { in tegra30_clock_init()
1330 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX, in tegra30_clock_init()
1335 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq, in tegra30_clock_init()
1344 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks, in tegra30_clock_init()
1370 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, in tegra30_car_probe()
1375 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, in tegra30_car_probe()
1380 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, in tegra30_car_probe()
1388 clk_base + SCLK_BURST_POLICY, in tegra30_car_probe()