Lines Matching refs:dt_id
539 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
540 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
541 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
542 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
543 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
544 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
545 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
546 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
547 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
548 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
549 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
550 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
551 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
552 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
553 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
554 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
555 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
556 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
557 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
558 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
559 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
560 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
561 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
562 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
563 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
564 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
565 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
566 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
567 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
568 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
569 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
570 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
571 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
572 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
573 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
574 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
575 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
576 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
577 { .con_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
578 { .con_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
579 { .con_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
580 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
581 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
582 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
583 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
584 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
585 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
586 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
587 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
588 { .con_id = "osc", .dt_id = TEGRA30_CLK_OSC },
589 { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 },
590 { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 },
591 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
592 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
593 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
594 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
595 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
596 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
597 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
598 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
599 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
600 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
601 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
602 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
603 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
604 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
605 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
606 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
607 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
608 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
609 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
610 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
611 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
612 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
613 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
614 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
615 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
616 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
617 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
618 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
619 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
620 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
621 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
622 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
623 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
624 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
625 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
626 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
627 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
628 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
629 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
630 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
631 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
632 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
633 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
634 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
635 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
636 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
637 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
638 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
639 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
640 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
641 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
642 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
643 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
644 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
645 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
646 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
647 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
648 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
649 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
650 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
651 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
652 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
653 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
654 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
655 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
656 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
657 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
658 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
659 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
660 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
661 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
662 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
663 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
664 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
665 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
666 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
667 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
668 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
669 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
670 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
671 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
672 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
673 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
674 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
675 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
676 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
677 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
678 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
679 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
680 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
681 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
682 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
683 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
684 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
685 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
689 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
690 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
691 [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
692 [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
693 [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
694 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
695 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
696 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
697 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
698 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
699 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
700 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
701 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
702 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
703 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
704 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
705 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
706 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
707 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
708 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
709 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
710 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
711 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
712 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
713 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
714 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
715 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
716 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
717 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
718 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
719 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
720 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
721 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
722 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
723 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
724 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
725 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
726 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
727 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
728 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
729 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
730 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
731 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
732 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
733 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
734 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
735 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
736 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
737 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
738 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
739 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
740 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
741 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
742 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
743 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
744 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
745 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
746 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
747 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
748 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
749 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
750 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
751 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
752 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
753 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
754 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
755 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
756 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
757 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
758 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
759 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
760 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
761 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
762 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
763 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
764 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
765 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
766 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
767 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
768 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
769 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
770 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
771 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
772 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
773 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
774 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
775 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
776 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
777 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
778 [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
779 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
780 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
781 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
782 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
783 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
784 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
785 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
786 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
787 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
788 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
789 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
790 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
791 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
792 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
793 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
794 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
795 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
796 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
797 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
798 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
799 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
800 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
801 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
802 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
803 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
804 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
805 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
806 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
807 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
808 [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
809 [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false },