Lines Matching refs:TI_CLK_MUX
39 { 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
75 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
76 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
77 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
98 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
103 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
108 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
113 { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
124 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
156 { 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
220 { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
221 { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
322 { 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
323 { 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
350 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
367 { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
456 { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
457 { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
482 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
487 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
492 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
497 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
502 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
507 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
558 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
575 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
581 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
586 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
591 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
596 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
601 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
667 { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
673 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
674 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
675 { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
680 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
681 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
686 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
687 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
692 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
693 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
698 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
699 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
704 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
709 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
714 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
719 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
720 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
725 { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
726 { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
753 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
758 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
763 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
768 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
787 { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
792 { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
803 { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },