Lines Matching refs:clk_hw
12 struct clk_hw hw;
27 struct clk_hw hw;
202 struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
205 struct clk_hw *hw, const char *con);
212 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
222 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
246 int omap2_init_clk_clkdm(struct clk_hw *hw);
247 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
248 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
250 int omap2_dflt_clk_enable(struct clk_hw *hw);
251 void omap2_dflt_clk_disable(struct clk_hw *hw);
252 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
263 u8 omap2_init_dpll_parent(struct clk_hw *hw);
264 int omap3_noncore_dpll_enable(struct clk_hw *hw);
265 void omap3_noncore_dpll_disable(struct clk_hw *hw);
266 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
267 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
269 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
273 int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
275 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
277 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
287 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
288 int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
290 int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
292 int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
296 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
298 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
301 int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,