Lines Matching refs:offset
44 u64 offset; in nitrox_config_emu_unit() local
58 offset = EMU_WD_INT_ENA_W1SX(i); in nitrox_config_emu_unit()
59 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
60 offset = EMU_GE_INT_ENA_W1SX(i); in nitrox_config_emu_unit()
61 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
70 u64 offset; in reset_pkt_input_ring() local
73 offset = NPS_PKT_IN_INSTR_CTLX(ring); in reset_pkt_input_ring()
74 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
76 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
81 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
88 offset = NPS_PKT_IN_DONE_CNTSX(ring); in reset_pkt_input_ring()
89 pkt_in_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
90 nitrox_write_csr(ndev, offset, pkt_in_cnts.value); in reset_pkt_input_ring()
98 u64 offset; in enable_pkt_input_ring() local
101 offset = NPS_PKT_IN_INSTR_CTLX(ring); in enable_pkt_input_ring()
102 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
105 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in enable_pkt_input_ring()
109 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_input_ring()
128 u64 offset; in nitrox_config_pkt_input_rings() local
137 offset = NPS_PKT_IN_INSTR_BADDRX(i); in nitrox_config_pkt_input_rings()
138 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_pkt_input_rings()
141 offset = NPS_PKT_IN_INSTR_RSIZEX(i); in nitrox_config_pkt_input_rings()
144 nitrox_write_csr(ndev, offset, pkt_in_rsize.value); in nitrox_config_pkt_input_rings()
147 offset = NPS_PKT_IN_INT_LEVELSX(i); in nitrox_config_pkt_input_rings()
148 nitrox_write_csr(ndev, offset, 0xffffffff); in nitrox_config_pkt_input_rings()
151 offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i); in nitrox_config_pkt_input_rings()
154 nitrox_write_csr(ndev, offset, pkt_in_dbell.value); in nitrox_config_pkt_input_rings()
166 u64 offset; in reset_pkt_solicit_port() local
169 offset = NPS_PKT_SLC_CTLX(port); in reset_pkt_solicit_port()
170 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
172 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in reset_pkt_solicit_port()
178 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
185 offset = NPS_PKT_SLC_CNTSX(port); in reset_pkt_solicit_port()
186 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset); in reset_pkt_solicit_port()
187 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value); in reset_pkt_solicit_port()
195 u64 offset; in enable_pkt_solicit_port() local
197 offset = NPS_PKT_SLC_CTLX(port); in enable_pkt_solicit_port()
207 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value); in enable_pkt_solicit_port()
211 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset); in enable_pkt_solicit_port()
221 u64 offset; in config_pkt_solicit_port() local
226 offset = NPS_PKT_SLC_INT_LEVELSX(port); in config_pkt_solicit_port()
230 nitrox_write_csr(ndev, offset, pkt_slc_int.value); in config_pkt_solicit_port()
315 u64 offset; in reset_aqm_ring() local
318 offset = AQMQ_ENX(ring); in reset_aqm_ring()
321 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in reset_aqm_ring()
325 offset = AQMQ_ACTIVITY_STATX(ring); in reset_aqm_ring()
327 activity_stat.value = nitrox_read_csr(ndev, offset); in reset_aqm_ring()
334 offset = AQMQ_CMP_CNTX(ring); in reset_aqm_ring()
335 cmp_cnt.value = nitrox_read_csr(ndev, offset); in reset_aqm_ring()
336 nitrox_write_csr(ndev, offset, cmp_cnt.value); in reset_aqm_ring()
343 u64 offset; in enable_aqm_ring() local
345 offset = AQMQ_ENX(ring); in enable_aqm_ring()
348 nitrox_write_csr(ndev, offset, aqmq_en_reg.value); in enable_aqm_ring()
361 u64 offset; in nitrox_config_aqm_rings() local
367 offset = AQMQ_DRBLX(ring); in nitrox_config_aqm_rings()
370 nitrox_write_csr(ndev, offset, drbl.value); in nitrox_config_aqm_rings()
375 offset = AQMQ_NXT_CMDX(ring); in nitrox_config_aqm_rings()
376 nitrox_write_csr(ndev, offset, 0ULL); in nitrox_config_aqm_rings()
379 offset = AQMQ_BADRX(ring); in nitrox_config_aqm_rings()
380 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_aqm_rings()
383 offset = AQMQ_QSZX(ring); in nitrox_config_aqm_rings()
386 nitrox_write_csr(ndev, offset, qsize.value); in nitrox_config_aqm_rings()
389 offset = AQMQ_CMP_THRX(ring); in nitrox_config_aqm_rings()
392 nitrox_write_csr(ndev, offset, cmp_thr.value); in nitrox_config_aqm_rings()
443 u64 offset; in nitrox_config_rand_unit() local
445 offset = EFL_RNM_CTL_STATUS; in nitrox_config_rand_unit()
446 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_rand_unit()
449 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value); in nitrox_config_rand_unit()
458 u64 offset; in nitrox_config_efl_unit() local
461 offset = EFL_CORE_INT_ENA_W1SX(i); in nitrox_config_efl_unit()
466 nitrox_write_csr(ndev, offset, efl_core_int.value); in nitrox_config_efl_unit()
468 offset = EFL_CORE_VF_ERR_INT0_ENA_W1SX(i); in nitrox_config_efl_unit()
469 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
470 offset = EFL_CORE_VF_ERR_INT1_ENA_W1SX(i); in nitrox_config_efl_unit()
471 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
479 u64 offset; in nitrox_config_bmi_unit() local
482 offset = BMI_CTL; in nitrox_config_bmi_unit()
483 bmi_ctl.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmi_unit()
487 nitrox_write_csr(ndev, offset, bmi_ctl.value); in nitrox_config_bmi_unit()
490 offset = BMI_INT_ENA_W1S; in nitrox_config_bmi_unit()
495 nitrox_write_csr(ndev, offset, bmi_int_ena.value); in nitrox_config_bmi_unit()
501 u64 offset; in nitrox_config_bmo_unit() local
504 offset = BMO_CTL2; in nitrox_config_bmo_unit()
505 bmo_ctl2.value = nitrox_read_csr(ndev, offset); in nitrox_config_bmo_unit()
507 nitrox_write_csr(ndev, offset, bmo_ctl2.value); in nitrox_config_bmo_unit()
515 u64 offset; in invalidate_lbc() local
518 offset = LBC_INVAL_CTL; in invalidate_lbc()
519 lbc_ctl.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
521 nitrox_write_csr(ndev, offset, lbc_ctl.value); in invalidate_lbc()
523 offset = LBC_INVAL_STATUS; in invalidate_lbc()
525 lbc_stat.value = nitrox_read_csr(ndev, offset); in invalidate_lbc()
535 u64 offset; in nitrox_config_lbc_unit() local
540 offset = LBC_INT_ENA_W1S; in nitrox_config_lbc_unit()
546 nitrox_write_csr(ndev, offset, lbc_int_ena.value); in nitrox_config_lbc_unit()
548 offset = LBC_PLM_VF1_64_INT_ENA_W1S; in nitrox_config_lbc_unit()
549 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
550 offset = LBC_PLM_VF65_128_INT_ENA_W1S; in nitrox_config_lbc_unit()
551 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
553 offset = LBC_ELM_VF1_64_INT_ENA_W1S; in nitrox_config_lbc_unit()
554 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
555 offset = LBC_ELM_VF65_128_INT_ENA_W1S; in nitrox_config_lbc_unit()
556 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
615 u64 offset; in nitrox_get_hwinfo() local
618 offset = RST_BOOT; in nitrox_get_hwinfo()
619 rst_boot.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
623 offset = EMU_FUSE_MAPX(i); in nitrox_get_hwinfo()
624 emu_fuse.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()
633 offset = FUS_DAT1; in nitrox_get_hwinfo()
634 fus_dat1.value = nitrox_read_csr(ndev, offset); in nitrox_get_hwinfo()