Lines Matching refs:ULL
290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
291 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
292 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
295 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL)); in enable_nps_pkt_interrupts()
376 nitrox_write_csr(ndev, offset, 0ULL); in nitrox_config_aqm_rings()
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
403 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
405 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
406 nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
407 nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
408 nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
409 nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL)); in enable_aqm_interrupts()
469 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
471 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_efl_unit()
549 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
551 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
554 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
556 nitrox_write_csr(ndev, offset, (~0ULL)); in nitrox_config_lbc_unit()
655 u64 value = ~0ULL; in enable_pf2vf_mbox_interrupts()
669 u64 value = ~0ULL; in disable_pf2vf_mbox_interrupts()