Lines Matching refs:dw
28 static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) in __dw_regs() argument
30 return dw->chip->reg_base; in __dw_regs()
33 #define SET_32(dw, name, value) \ argument
34 writel(value, &(__dw_regs(dw)->name))
36 #define GET_32(dw, name) \ argument
37 readl(&(__dw_regs(dw)->name))
39 #define SET_RW_32(dw, dir, name, value) \ argument
42 SET_32(dw, wr_##name, value); \
44 SET_32(dw, rd_##name, value); \
47 #define GET_RW_32(dw, dir, name) \ argument
49 ? GET_32(dw, wr_##name) \
50 : GET_32(dw, rd_##name))
52 #define SET_BOTH_32(dw, name, value) \ argument
54 SET_32(dw, wr_##name, value); \
55 SET_32(dw, rd_##name, value); \
58 #define SET_64(dw, name, value) \ argument
59 writeq(value, &(__dw_regs(dw)->name))
61 #define GET_64(dw, name) \ argument
62 readq(&(__dw_regs(dw)->name))
64 #define SET_RW_64(dw, dir, name, value) \ argument
67 SET_64(dw, wr_##name, value); \
69 SET_64(dw, rd_##name, value); \
72 #define GET_RW_64(dw, dir, name) \ argument
74 ? GET_64(dw, wr_##name) \
75 : GET_64(dw, rd_##name))
77 #define SET_BOTH_64(dw, name, value) \ argument
79 SET_64(dw, wr_##name, value); \
80 SET_64(dw, rd_##name, value); \
83 #define SET_COMPAT(dw, name, value) \ argument
84 writel(value, &(__dw_regs(dw)->type.unroll.name))
86 #define SET_RW_COMPAT(dw, dir, name, value) \ argument
89 SET_COMPAT(dw, wr_##name, value); \
91 SET_COMPAT(dw, rd_##name, value); \
95 __dw_ch_regs(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch) in __dw_ch_regs() argument
97 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) in __dw_ch_regs()
98 return &(__dw_regs(dw)->type.legacy.ch); in __dw_ch_regs()
101 return &__dw_regs(dw)->type.unroll.ch[ch].wr; in __dw_ch_regs()
103 return &__dw_regs(dw)->type.unroll.ch[ch].rd; in __dw_ch_regs()
106 static inline void writel_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, in writel_ch() argument
109 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) { in writel_ch()
113 raw_spin_lock_irqsave(&dw->lock, flags); in writel_ch()
120 &(__dw_regs(dw)->type.legacy.viewport_sel)); in writel_ch()
123 raw_spin_unlock_irqrestore(&dw->lock, flags); in writel_ch()
129 static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, in readl_ch() argument
134 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) { in readl_ch()
138 raw_spin_lock_irqsave(&dw->lock, flags); in readl_ch()
145 &(__dw_regs(dw)->type.legacy.viewport_sel)); in readl_ch()
148 raw_spin_unlock_irqrestore(&dw->lock, flags); in readl_ch()
156 #define SET_CH_32(dw, dir, ch, name, value) \ argument
157 writel_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
159 #define GET_CH_32(dw, dir, ch, name) \ argument
160 readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
162 static inline void writeq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, in writeq_ch() argument
165 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) { in writeq_ch()
169 raw_spin_lock_irqsave(&dw->lock, flags); in writeq_ch()
176 &(__dw_regs(dw)->type.legacy.viewport_sel)); in writeq_ch()
179 raw_spin_unlock_irqrestore(&dw->lock, flags); in writeq_ch()
185 static inline u64 readq_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch, in readq_ch() argument
190 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) { in readq_ch()
194 raw_spin_lock_irqsave(&dw->lock, flags); in readq_ch()
201 &(__dw_regs(dw)->type.legacy.viewport_sel)); in readq_ch()
204 raw_spin_unlock_irqrestore(&dw->lock, flags); in readq_ch()
212 #define SET_CH_64(dw, dir, ch, name, value) \ argument
213 writeq_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
215 #define GET_CH_64(dw, dir, ch, name) \ argument
216 readq_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
219 void dw_edma_v0_core_off(struct dw_edma *dw) in dw_edma_v0_core_off() argument
221 SET_BOTH_32(dw, int_mask, in dw_edma_v0_core_off()
223 SET_BOTH_32(dw, int_clear, in dw_edma_v0_core_off()
225 SET_BOTH_32(dw, engine_en, 0); in dw_edma_v0_core_off()
228 u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir) in dw_edma_v0_core_ch_count() argument
234 GET_32(dw, ctrl)); in dw_edma_v0_core_ch_count()
237 GET_32(dw, ctrl)); in dw_edma_v0_core_ch_count()
247 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_ch_status() local
251 GET_CH_32(dw, chan->dir, chan->id, ch_control1)); in dw_edma_v0_core_ch_status()
263 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_clear_done_int() local
265 SET_RW_32(dw, chan->dir, int_clear, in dw_edma_v0_core_clear_done_int()
271 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_clear_abort_int() local
273 SET_RW_32(dw, chan->dir, int_clear, in dw_edma_v0_core_clear_abort_int()
277 u32 dw_edma_v0_core_status_done_int(struct dw_edma *dw, enum dw_edma_dir dir) in dw_edma_v0_core_status_done_int() argument
280 GET_RW_32(dw, dir, int_status)); in dw_edma_v0_core_status_done_int()
283 u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir) in dw_edma_v0_core_status_abort_int() argument
286 GET_RW_32(dw, dir, int_status)); in dw_edma_v0_core_status_abort_int()
294 if (chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { in dw_edma_v0_write_ll_data()
316 if (chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { in dw_edma_v0_write_ll_link()
344 if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) in dw_edma_v0_core_write_chunk()
362 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_start() local
369 SET_RW_32(dw, chan->dir, engine_en, BIT(0)); in dw_edma_v0_core_start()
370 if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) { in dw_edma_v0_core_start()
373 SET_RW_COMPAT(dw, chan->dir, ch0_pwr_en, in dw_edma_v0_core_start()
377 SET_RW_COMPAT(dw, chan->dir, ch1_pwr_en, in dw_edma_v0_core_start()
381 SET_RW_COMPAT(dw, chan->dir, ch2_pwr_en, in dw_edma_v0_core_start()
385 SET_RW_COMPAT(dw, chan->dir, ch3_pwr_en, in dw_edma_v0_core_start()
389 SET_RW_COMPAT(dw, chan->dir, ch4_pwr_en, in dw_edma_v0_core_start()
393 SET_RW_COMPAT(dw, chan->dir, ch5_pwr_en, in dw_edma_v0_core_start()
397 SET_RW_COMPAT(dw, chan->dir, ch6_pwr_en, in dw_edma_v0_core_start()
401 SET_RW_COMPAT(dw, chan->dir, ch7_pwr_en, in dw_edma_v0_core_start()
407 tmp = GET_RW_32(dw, chan->dir, int_mask); in dw_edma_v0_core_start()
410 SET_RW_32(dw, chan->dir, int_mask, tmp); in dw_edma_v0_core_start()
412 tmp = GET_RW_32(dw, chan->dir, linked_list_err_en); in dw_edma_v0_core_start()
414 SET_RW_32(dw, chan->dir, linked_list_err_en, tmp); in dw_edma_v0_core_start()
416 SET_CH_32(dw, chan->dir, chan->id, ch_control1, in dw_edma_v0_core_start()
420 SET_CH_32(dw, chan->dir, chan->id, llp.lsb, in dw_edma_v0_core_start()
422 SET_CH_32(dw, chan->dir, chan->id, llp.msb, in dw_edma_v0_core_start()
426 SET_RW_32(dw, chan->dir, doorbell, in dw_edma_v0_core_start()
432 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_device_config() local
436 SET_RW_32(dw, chan->dir, done_imwr.lsb, chan->msi.address_lo); in dw_edma_v0_core_device_config()
437 SET_RW_32(dw, chan->dir, done_imwr.msb, chan->msi.address_hi); in dw_edma_v0_core_device_config()
439 SET_RW_32(dw, chan->dir, abort_imwr.lsb, chan->msi.address_lo); in dw_edma_v0_core_device_config()
440 SET_RW_32(dw, chan->dir, abort_imwr.msb, chan->msi.address_hi); in dw_edma_v0_core_device_config()
445 tmp = GET_RW_32(dw, chan->dir, ch01_imwr_data); in dw_edma_v0_core_device_config()
450 tmp = GET_RW_32(dw, chan->dir, ch23_imwr_data); in dw_edma_v0_core_device_config()
455 tmp = GET_RW_32(dw, chan->dir, ch45_imwr_data); in dw_edma_v0_core_device_config()
460 tmp = GET_RW_32(dw, chan->dir, ch67_imwr_data); in dw_edma_v0_core_device_config()
479 SET_RW_32(dw, chan->dir, ch01_imwr_data, tmp); in dw_edma_v0_core_device_config()
484 SET_RW_32(dw, chan->dir, ch23_imwr_data, tmp); in dw_edma_v0_core_device_config()
489 SET_RW_32(dw, chan->dir, ch45_imwr_data, tmp); in dw_edma_v0_core_device_config()
494 SET_RW_32(dw, chan->dir, ch67_imwr_data, tmp); in dw_edma_v0_core_device_config()
502 void dw_edma_v0_core_debugfs_on(struct dw_edma *dw) in dw_edma_v0_core_debugfs_on() argument
504 dw_edma_v0_debugfs_on(dw); in dw_edma_v0_core_debugfs_on()