Lines Matching refs:dst_info
90 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
91 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
92 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
104 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
105 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
106 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
1397 return num_elt * d40c->dma_cfg.dst_info.data_width; in d40_residue()
1730 d40_psize_2_burst_size(is_log, conf->dst_info.psize) * in d40_validate_conf()
1731 conf->dst_info.data_width) { in d40_validate_conf()
2116 struct stedma40_half_channel_info *dst_info = &cfg->dst_info; in d40_prep_sg_log() local
2124 dst_info->data_width); in d40_prep_sg_log()
2130 dst_info->data_width, in d40_prep_sg_log()
2144 struct stedma40_half_channel_info *dst_info = &cfg->dst_info; in d40_prep_sg_phy() local
2155 src_info, dst_info, flags); in d40_prep_sg_phy()
2161 dst_info, src_info, flags); in d40_prep_sg_phy()
2183 cfg->dst_info.data_width); in d40_prep_desc()
2368 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags); in d40_xlate()
2747 cfg->dst_info.data_width = dst_addr_width; in d40_set_runtime_config_write()
2754 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info, in d40_set_runtime_config_write()