Lines Matching refs:tdc
177 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
241 static inline void tdc_write(struct tegra_dma_channel *tdc, in tdc_write() argument
244 writel(val, tdc->chan_addr + reg); in tdc_write()
247 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg) in tdc_read() argument
249 return readl(tdc->chan_addr + reg); in tdc_read()
263 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) in tdc2dev() argument
265 return &tdc->dma_chan.dev->device; in tdc2dev()
271 static struct tegra_dma_desc *tegra_dma_desc_get(struct tegra_dma_channel *tdc) in tegra_dma_desc_get() argument
276 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_desc_get()
279 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { in tegra_dma_desc_get()
282 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_get()
288 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_get()
295 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan); in tegra_dma_desc_get()
302 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc, in tegra_dma_desc_put() argument
307 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_desc_put()
309 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req); in tegra_dma_desc_put()
310 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in tegra_dma_desc_put()
311 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_desc_put()
315 tegra_dma_sg_req_get(struct tegra_dma_channel *tdc) in tegra_dma_sg_req_get() argument
320 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_sg_req_get()
321 if (!list_empty(&tdc->free_sg_req)) { in tegra_dma_sg_req_get()
322 sg_req = list_first_entry(&tdc->free_sg_req, typeof(*sg_req), in tegra_dma_sg_req_get()
325 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_sg_req_get()
328 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_sg_req_get()
338 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_slave_config() local
340 if (!list_empty(&tdc->pending_sg_req)) { in tegra_dma_slave_config()
341 dev_err(tdc2dev(tdc), "Configuration not allowed\n"); in tegra_dma_slave_config()
345 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
346 tdc->config_init = true; in tegra_dma_slave_config()
351 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc, in tegra_dma_global_pause() argument
354 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_pause()
358 if (tdc->tdma->global_pause_count == 0) { in tegra_dma_global_pause()
364 tdc->tdma->global_pause_count++; in tegra_dma_global_pause()
369 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc) in tegra_dma_global_resume() argument
371 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_global_resume()
375 if (WARN_ON(tdc->tdma->global_pause_count == 0)) in tegra_dma_global_resume()
378 if (--tdc->tdma->global_pause_count == 0) in tegra_dma_global_resume()
386 static void tegra_dma_pause(struct tegra_dma_channel *tdc, in tegra_dma_pause() argument
389 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_pause()
392 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, in tegra_dma_pause()
397 tegra_dma_global_pause(tdc, wait_for_burst_complete); in tegra_dma_pause()
401 static void tegra_dma_resume(struct tegra_dma_channel *tdc) in tegra_dma_resume() argument
403 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_resume()
406 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0); in tegra_dma_resume()
408 tegra_dma_global_resume(tdc); in tegra_dma_resume()
411 static void tegra_dma_stop(struct tegra_dma_channel *tdc) in tegra_dma_stop() argument
416 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR); in tegra_dma_stop()
418 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
422 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); in tegra_dma_stop()
425 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_stop()
427 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); in tegra_dma_stop()
428 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); in tegra_dma_stop()
430 tdc->busy = false; in tegra_dma_stop()
433 static void tegra_dma_start(struct tegra_dma_channel *tdc, in tegra_dma_start() argument
438 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
439 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq); in tegra_dma_start()
440 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr); in tegra_dma_start()
441 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq); in tegra_dma_start()
442 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr); in tegra_dma_start()
443 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_start()
444 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
447 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, in tegra_dma_start()
451 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc, in tegra_dma_configure_for_next() argument
467 tegra_dma_pause(tdc, false); in tegra_dma_configure_for_next()
468 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_configure_for_next()
475 dev_err(tdc2dev(tdc), in tegra_dma_configure_for_next()
477 tegra_dma_resume(tdc); in tegra_dma_configure_for_next()
482 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr); in tegra_dma_configure_for_next()
483 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr); in tegra_dma_configure_for_next()
484 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_configure_for_next()
485 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, in tegra_dma_configure_for_next()
487 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, in tegra_dma_configure_for_next()
492 tegra_dma_resume(tdc); in tegra_dma_configure_for_next()
495 static void tdc_start_head_req(struct tegra_dma_channel *tdc) in tdc_start_head_req() argument
499 sg_req = list_first_entry(&tdc->pending_sg_req, typeof(*sg_req), node); in tdc_start_head_req()
500 tegra_dma_start(tdc, sg_req); in tdc_start_head_req()
503 tdc->busy = true; in tdc_start_head_req()
506 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc) in tdc_configure_next_head_desc() argument
510 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); in tdc_configure_next_head_desc()
511 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) { in tdc_configure_next_head_desc()
514 tegra_dma_configure_for_next(tdc, hnsgreq); in tdc_configure_next_head_desc()
519 get_current_xferred_count(struct tegra_dma_channel *tdc, in get_current_xferred_count() argument
526 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc) in tegra_dma_abort_all() argument
531 while (!list_empty(&tdc->pending_sg_req)) { in tegra_dma_abort_all()
532 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), in tegra_dma_abort_all()
534 list_move_tail(&sgreq->node, &tdc->free_sg_req); in tegra_dma_abort_all()
538 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in tegra_dma_abort_all()
543 &tdc->cb_desc); in tegra_dma_abort_all()
547 tdc->isr_handler = NULL; in tegra_dma_abort_all()
550 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc, in handle_continuous_head_request() argument
560 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); in handle_continuous_head_request()
562 tegra_dma_stop(tdc); in handle_continuous_head_request()
563 pm_runtime_put(tdc->tdma->dev); in handle_continuous_head_request()
564 dev_err(tdc2dev(tdc), "DMA transfer underflow, aborting DMA\n"); in handle_continuous_head_request()
565 tegra_dma_abort_all(tdc); in handle_continuous_head_request()
571 tdc_configure_next_head_desc(tdc); in handle_continuous_head_request()
576 static void handle_once_dma_done(struct tegra_dma_channel *tdc, in handle_once_dma_done() argument
582 tdc->busy = false; in handle_once_dma_done()
583 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); in handle_once_dma_done()
592 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); in handle_once_dma_done()
594 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); in handle_once_dma_done()
596 list_add_tail(&sgreq->node, &tdc->free_sg_req); in handle_once_dma_done()
602 if (list_empty(&tdc->pending_sg_req)) { in handle_once_dma_done()
603 pm_runtime_put(tdc->tdma->dev); in handle_once_dma_done()
607 tdc_start_head_req(tdc); in handle_once_dma_done()
610 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc, in handle_cont_sngl_cycle_dma_done() argument
617 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); in handle_cont_sngl_cycle_dma_done()
626 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); in handle_cont_sngl_cycle_dma_done()
632 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) { in handle_cont_sngl_cycle_dma_done()
633 list_move_tail(&sgreq->node, &tdc->pending_sg_req); in handle_cont_sngl_cycle_dma_done()
635 st = handle_continuous_head_request(tdc, to_terminate); in handle_cont_sngl_cycle_dma_done()
643 struct tegra_dma_channel *tdc = from_tasklet(tdc, t, tasklet); in tegra_dma_tasklet() local
649 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tasklet()
650 while (!list_empty(&tdc->cb_desc)) { in tegra_dma_tasklet()
651 dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc), in tegra_dma_tasklet()
657 trace_tegra_dma_complete_cb(&tdc->dma_chan, cb_count, in tegra_dma_tasklet()
659 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tasklet()
662 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tasklet()
664 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tasklet()
669 struct tegra_dma_channel *tdc = dev_id; in tegra_dma_isr() local
672 spin_lock(&tdc->lock); in tegra_dma_isr()
674 trace_tegra_dma_isr(&tdc->dma_chan, irq); in tegra_dma_isr()
675 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_isr()
677 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); in tegra_dma_isr()
678 tdc->isr_handler(tdc, false); in tegra_dma_isr()
679 tasklet_schedule(&tdc->tasklet); in tegra_dma_isr()
680 wake_up_all(&tdc->wq); in tegra_dma_isr()
681 spin_unlock(&tdc->lock); in tegra_dma_isr()
685 spin_unlock(&tdc->lock); in tegra_dma_isr()
686 dev_info(tdc2dev(tdc), "Interrupt already served status 0x%08x\n", in tegra_dma_isr()
695 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan); in tegra_dma_tx_submit() local
699 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tx_submit()
702 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req); in tegra_dma_tx_submit()
703 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_submit()
710 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_issue_pending() local
714 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_issue_pending()
715 if (list_empty(&tdc->pending_sg_req)) { in tegra_dma_issue_pending()
716 dev_err(tdc2dev(tdc), "No DMA request\n"); in tegra_dma_issue_pending()
719 if (!tdc->busy) { in tegra_dma_issue_pending()
720 err = pm_runtime_resume_and_get(tdc->tdma->dev); in tegra_dma_issue_pending()
722 dev_err(tdc2dev(tdc), "Failed to enable DMA\n"); in tegra_dma_issue_pending()
726 tdc_start_head_req(tdc); in tegra_dma_issue_pending()
729 if (tdc->cyclic) { in tegra_dma_issue_pending()
735 tdc_configure_next_head_desc(tdc); in tegra_dma_issue_pending()
739 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_issue_pending()
744 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_terminate_all() local
751 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_terminate_all()
753 if (!tdc->busy) in tegra_dma_terminate_all()
757 tegra_dma_pause(tdc, true); in tegra_dma_terminate_all()
759 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_terminate_all()
761 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__); in tegra_dma_terminate_all()
762 tdc->isr_handler(tdc, true); in tegra_dma_terminate_all()
763 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_terminate_all()
765 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_terminate_all()
766 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); in tegra_dma_terminate_all()
770 was_busy = tdc->busy; in tegra_dma_terminate_all()
771 tegra_dma_stop(tdc); in tegra_dma_terminate_all()
773 if (!list_empty(&tdc->pending_sg_req) && was_busy) { in tegra_dma_terminate_all()
774 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), in tegra_dma_terminate_all()
777 get_current_xferred_count(tdc, sgreq, wcount); in tegra_dma_terminate_all()
779 tegra_dma_resume(tdc); in tegra_dma_terminate_all()
781 pm_runtime_put(tdc->tdma->dev); in tegra_dma_terminate_all()
782 wake_up_all(&tdc->wq); in tegra_dma_terminate_all()
785 tegra_dma_abort_all(tdc); in tegra_dma_terminate_all()
787 while (!list_empty(&tdc->cb_desc)) { in tegra_dma_terminate_all()
788 dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc), in tegra_dma_terminate_all()
793 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_terminate_all()
798 static bool tegra_dma_eoc_interrupt_deasserted(struct tegra_dma_channel *tdc) in tegra_dma_eoc_interrupt_deasserted() argument
803 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_eoc_interrupt_deasserted()
804 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_eoc_interrupt_deasserted()
805 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_eoc_interrupt_deasserted()
812 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_synchronize() local
815 err = pm_runtime_resume_and_get(tdc->tdma->dev); in tegra_dma_synchronize()
817 dev_err(tdc2dev(tdc), "Failed to synchronize DMA: %d\n", err); in tegra_dma_synchronize()
826 wait_event(tdc->wq, tegra_dma_eoc_interrupt_deasserted(tdc)); in tegra_dma_synchronize()
828 tasklet_kill(&tdc->tasklet); in tegra_dma_synchronize()
830 pm_runtime_put(tdc->tdma->dev); in tegra_dma_synchronize()
833 static unsigned int tegra_dma_sg_bytes_xferred(struct tegra_dma_channel *tdc, in tegra_dma_sg_bytes_xferred() argument
838 if (!list_is_first(&sg_req->node, &tdc->pending_sg_req)) in tegra_dma_sg_bytes_xferred()
841 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_sg_bytes_xferred()
842 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); in tegra_dma_sg_bytes_xferred()
844 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); in tegra_dma_sg_bytes_xferred()
846 if (!tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_sg_bytes_xferred()
852 wcount = get_current_xferred_count(tdc, sg_req, wcount); in tegra_dma_sg_bytes_xferred()
896 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_tx_status() local
908 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_tx_status()
911 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { in tegra_dma_tx_status()
919 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) { in tegra_dma_tx_status()
922 bytes = tegra_dma_sg_bytes_xferred(tdc, sg_req); in tegra_dma_tx_status()
928 dev_dbg(tdc2dev(tdc), "cookie %d not found\n", cookie); in tegra_dma_tx_status()
939 trace_tegra_dma_tx_status(&tdc->dma_chan, cookie, txstate); in tegra_dma_tx_status()
940 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_tx_status()
945 static inline unsigned int get_bus_width(struct tegra_dma_channel *tdc, in get_bus_width() argument
958 dev_warn(tdc2dev(tdc), in get_bus_width()
964 static inline unsigned int get_burst_size(struct tegra_dma_channel *tdc, in get_burst_size() argument
995 static int get_transfer_param(struct tegra_dma_channel *tdc, in get_transfer_param() argument
1005 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
1006 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
1007 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
1008 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
1013 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
1014 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
1015 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
1016 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
1021 dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); in get_transfer_param()
1028 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc, in tegra_dma_prep_wcount() argument
1034 if (tdc->tdma->chip_data->support_separate_wcount_reg) in tegra_dma_prep_wcount()
1048 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_slave_sg() local
1058 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
1059 dev_err(tdc2dev(tdc), "DMA channel is not configured\n"); in tegra_dma_prep_slave_sg()
1063 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len); in tegra_dma_prep_slave_sg()
1067 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, in tegra_dma_prep_slave_sg()
1080 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { in tegra_dma_prep_slave_sg()
1082 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; in tegra_dma_prep_slave_sg()
1094 dma_desc = tegra_dma_desc_get(tdc); in tegra_dma_prep_slave_sg()
1096 dev_err(tdc2dev(tdc), "DMA descriptors not available\n"); in tegra_dma_prep_slave_sg()
1114 len > tdc->tdma->chip_data->max_dma_count) { in tegra_dma_prep_slave_sg()
1115 dev_err(tdc2dev(tdc), in tegra_dma_prep_slave_sg()
1117 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1121 sg_req = tegra_dma_sg_req_get(tdc); in tegra_dma_prep_slave_sg()
1123 dev_err(tdc2dev(tdc), "DMA sg-req not available\n"); in tegra_dma_prep_slave_sg()
1124 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1128 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len); in tegra_dma_prep_slave_sg()
1134 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); in tegra_dma_prep_slave_sg()
1152 if (!tdc->isr_handler) { in tegra_dma_prep_slave_sg()
1153 tdc->isr_handler = handle_once_dma_done; in tegra_dma_prep_slave_sg()
1154 tdc->cyclic = false; in tegra_dma_prep_slave_sg()
1156 if (tdc->cyclic) { in tegra_dma_prep_slave_sg()
1157 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n"); in tegra_dma_prep_slave_sg()
1158 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_slave_sg()
1173 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_cyclic() local
1183 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n"); in tegra_dma_prep_dma_cyclic()
1187 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1188 dev_err(tdc2dev(tdc), "DMA slave is not configured\n"); in tegra_dma_prep_dma_cyclic()
1198 if (tdc->busy) { in tegra_dma_prep_dma_cyclic()
1199 dev_err(tdc2dev(tdc), "Request not allowed when DMA running\n"); in tegra_dma_prep_dma_cyclic()
1208 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n"); in tegra_dma_prep_dma_cyclic()
1214 len > tdc->tdma->chip_data->max_dma_count) { in tegra_dma_prep_dma_cyclic()
1215 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n"); in tegra_dma_prep_dma_cyclic()
1219 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, in tegra_dma_prep_dma_cyclic()
1228 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { in tegra_dma_prep_dma_cyclic()
1230 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; in tegra_dma_prep_dma_cyclic()
1242 dma_desc = tegra_dma_desc_get(tdc); in tegra_dma_prep_dma_cyclic()
1244 dev_err(tdc2dev(tdc), "not enough descriptors available\n"); in tegra_dma_prep_dma_cyclic()
1258 sg_req = tegra_dma_sg_req_get(tdc); in tegra_dma_prep_dma_cyclic()
1260 dev_err(tdc2dev(tdc), "DMA sg-req not available\n"); in tegra_dma_prep_dma_cyclic()
1261 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_dma_cyclic()
1265 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len); in tegra_dma_prep_dma_cyclic()
1269 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); in tegra_dma_prep_dma_cyclic()
1289 if (!tdc->isr_handler) { in tegra_dma_prep_dma_cyclic()
1290 tdc->isr_handler = handle_cont_sngl_cycle_dma_done; in tegra_dma_prep_dma_cyclic()
1291 tdc->cyclic = true; in tegra_dma_prep_dma_cyclic()
1293 if (!tdc->cyclic) { in tegra_dma_prep_dma_cyclic()
1294 dev_err(tdc2dev(tdc), "DMA configuration conflict\n"); in tegra_dma_prep_dma_cyclic()
1295 tegra_dma_desc_put(tdc, dma_desc); in tegra_dma_prep_dma_cyclic()
1305 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_alloc_chan_resources() local
1307 dma_cookie_init(&tdc->dma_chan); in tegra_dma_alloc_chan_resources()
1314 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_free_chan_resources() local
1323 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1326 tasklet_kill(&tdc->tasklet); in tegra_dma_free_chan_resources()
1328 list_splice_init(&tdc->pending_sg_req, &sg_req_list); in tegra_dma_free_chan_resources()
1329 list_splice_init(&tdc->free_sg_req, &sg_req_list); in tegra_dma_free_chan_resources()
1330 list_splice_init(&tdc->free_dma_desc, &dma_desc_list); in tegra_dma_free_chan_resources()
1331 INIT_LIST_HEAD(&tdc->cb_desc); in tegra_dma_free_chan_resources()
1332 tdc->config_init = false; in tegra_dma_free_chan_resources()
1333 tdc->isr_handler = NULL; in tegra_dma_free_chan_resources()
1348 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; in tegra_dma_free_chan_resources()
1355 struct tegra_dma_channel *tdc; in tegra_dma_of_xlate() local
1367 tdc = to_tegra_dma_chan(chan); in tegra_dma_of_xlate()
1368 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1489 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe() local
1492 tdc->chan_addr = tdma->base_addr + in tegra_dma_probe()
1502 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i); in tegra_dma_probe()
1504 tdc->name, tdc); in tegra_dma_probe()
1512 tdc->dma_chan.device = &tdma->dma_dev; in tegra_dma_probe()
1513 dma_cookie_init(&tdc->dma_chan); in tegra_dma_probe()
1514 list_add_tail(&tdc->dma_chan.device_node, in tegra_dma_probe()
1516 tdc->tdma = tdma; in tegra_dma_probe()
1517 tdc->id = i; in tegra_dma_probe()
1518 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; in tegra_dma_probe()
1520 tasklet_setup(&tdc->tasklet, tegra_dma_tasklet); in tegra_dma_probe()
1521 spin_lock_init(&tdc->lock); in tegra_dma_probe()
1522 init_waitqueue_head(&tdc->wq); in tegra_dma_probe()
1524 INIT_LIST_HEAD(&tdc->pending_sg_req); in tegra_dma_probe()
1525 INIT_LIST_HEAD(&tdc->free_sg_req); in tegra_dma_probe()
1526 INIT_LIST_HEAD(&tdc->free_dma_desc); in tegra_dma_probe()
1527 INIT_LIST_HEAD(&tdc->cb_desc); in tegra_dma_probe()
1626 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_dev_suspend() local
1628 tasklet_kill(&tdc->tasklet); in tegra_dma_dev_suspend()
1630 spin_lock_irqsave(&tdc->lock, flags); in tegra_dma_dev_suspend()
1631 busy = tdc->busy; in tegra_dma_dev_suspend()
1632 spin_unlock_irqrestore(&tdc->lock, flags); in tegra_dma_dev_suspend()