Lines Matching refs:cs_mode
1340 int cs_mode = 0; in f17_get_cs_mode() local
1343 cs_mode |= CS_EVEN_PRIMARY; in f17_get_cs_mode()
1346 cs_mode |= CS_ODD_PRIMARY; in f17_get_cs_mode()
1350 cs_mode |= CS_ODD_SECONDARY; in f17_get_cs_mode()
1363 cs_mode |= CS_3R_INTERLEAVE; in f17_get_cs_mode()
1366 return cs_mode; in f17_get_cs_mode()
1371 int dimm, size0, size1, cs0, cs1, cs_mode; in debug_display_dimm_sizes_df() local
1379 cs_mode = f17_get_cs_mode(dimm, ctrl, pvt); in debug_display_dimm_sizes_df()
1381 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0); in debug_display_dimm_sizes_df()
1382 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1); in debug_display_dimm_sizes_df()
1911 unsigned cs_mode, int cs_mask_nr) in k8_dbam_to_chip_select() argument
1916 WARN_ON(cs_mode > 11); in k8_dbam_to_chip_select()
1917 return ddr2_cs_size(cs_mode, dclr & WIDTH_128); in k8_dbam_to_chip_select()
1921 WARN_ON(cs_mode > 10); in k8_dbam_to_chip_select()
1947 diff = cs_mode/3 + (unsigned)(cs_mode > 5); in k8_dbam_to_chip_select()
1949 return 32 << (cs_mode - diff); in k8_dbam_to_chip_select()
1952 WARN_ON(cs_mode > 6); in k8_dbam_to_chip_select()
1953 return 32 << cs_mode; in k8_dbam_to_chip_select()
2015 unsigned cs_mode, int cs_mask_nr) in f10_dbam_to_chip_select() argument
2019 WARN_ON(cs_mode > 11); in f10_dbam_to_chip_select()
2022 return ddr3_cs_size(cs_mode, dclr & WIDTH_128); in f10_dbam_to_chip_select()
2024 return ddr2_cs_size(cs_mode, dclr & WIDTH_128); in f10_dbam_to_chip_select()
2031 unsigned cs_mode, int cs_mask_nr) in f15_dbam_to_chip_select() argument
2033 WARN_ON(cs_mode > 12); in f15_dbam_to_chip_select()
2035 return ddr3_cs_size(cs_mode, false); in f15_dbam_to_chip_select()
2040 unsigned cs_mode, int cs_mask_nr) in f15_m60h_dbam_to_chip_select() argument
2045 WARN_ON(cs_mode > 12); in f15_m60h_dbam_to_chip_select()
2048 if (cs_mode > 9) in f15_m60h_dbam_to_chip_select()
2051 cs_size = ddr4_cs_size(cs_mode); in f15_m60h_dbam_to_chip_select()
2057 cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply); in f15_m60h_dbam_to_chip_select()
2060 if (cs_mode == 0x1) in f15_m60h_dbam_to_chip_select()
2063 cs_size = ddr3_cs_size(cs_mode, false); in f15_m60h_dbam_to_chip_select()
2073 unsigned cs_mode, int cs_mask_nr) in f16_dbam_to_chip_select() argument
2075 WARN_ON(cs_mode > 12); in f16_dbam_to_chip_select()
2077 if (cs_mode == 6 || cs_mode == 8 || in f16_dbam_to_chip_select()
2078 cs_mode == 9 || cs_mode == 12) in f16_dbam_to_chip_select()
2081 return ddr3_cs_size(cs_mode, false); in f16_dbam_to_chip_select()
2085 unsigned int cs_mode, int csrow_nr) in f17_addr_mask_to_cs_size() argument
2093 if (!cs_mode) in f17_addr_mask_to_cs_size()
2097 if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1)) in f17_addr_mask_to_cs_size()
2101 if (!(cs_mode & CS_ODD) && (csrow_nr & 1)) in f17_addr_mask_to_cs_size()
2128 if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY)) in f17_addr_mask_to_cs_size()
2146 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE); in f17_addr_mask_to_cs_size()
3398 u32 cs_mode, nr_pages; in get_csrow_nr_pages() local
3402 cs_mode = DBAM_DIMM(csrow_nr, dbam); in get_csrow_nr_pages()
3404 cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt); in get_csrow_nr_pages()
3407 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in get_csrow_nr_pages()
3411 csrow_nr_orig, dct, cs_mode); in get_csrow_nr_pages()