Lines Matching refs:umc
1050 static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) in umc_normaddr_to_sysaddr() argument
1070 ctx.inst_id = umc; in umc_normaddr_to_sysaddr()
1073 if (df_indirect_read_instance(nid, 0, 0x1B4, umc, &ctx.tmp)) in umc_normaddr_to_sysaddr()
1087 if (df_indirect_read_instance(nid, 0, 0x110 + (8 * base), umc, &ctx.tmp)) in umc_normaddr_to_sysaddr()
1110 if (df_indirect_read_instance(nid, 0, 0x114 + (8 * base), umc, &ctx.tmp)) in umc_normaddr_to_sysaddr()
1166 if (df_indirect_read_instance(nid, 0, 0x50, umc, &ctx.tmp)) in umc_normaddr_to_sysaddr()
1266 if (pvt->umc) { in determine_edac_cap()
1270 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in determine_edac_cap()
1276 if (pvt->umc[i].umc_cfg & BIT(12)) in determine_edac_cap()
1392 struct amd64_umc *umc; in __dump_misc_regs_df() local
1397 umc = &pvt->umc[i]; in __dump_misc_regs_df()
1399 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); in __dump_misc_regs_df()
1400 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); in __dump_misc_regs_df()
1401 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); in __dump_misc_regs_df()
1402 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in __dump_misc_regs_df()
1409 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi); in __dump_misc_regs_df()
1412 i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", in __dump_misc_regs_df()
1413 (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); in __dump_misc_regs_df()
1415 i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); in __dump_misc_regs_df()
1417 i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); in __dump_misc_regs_df()
1419 i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); in __dump_misc_regs_df()
1421 if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) { in __dump_misc_regs_df()
1472 if (pvt->umc) in dump_misc_regs()
1492 int umc; in prep_chip_selects() local
1494 for_each_umc(umc) { in prep_chip_selects()
1495 pvt->csels[umc].b_cnt = 4; in prep_chip_selects()
1496 pvt->csels[umc].m_cnt = fam_type->flags.zn_regs_v2 ? 4 : 2; in prep_chip_selects()
1513 int cs, umc; in read_umc_base_mask() local
1515 for_each_umc(umc) { in read_umc_base_mask()
1516 umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR; in read_umc_base_mask()
1517 umc_base_reg_sec = get_umc_base(umc) + UMCCH_BASE_ADDR_SEC; in read_umc_base_mask()
1519 for_each_chip_select(cs, umc, pvt) { in read_umc_base_mask()
1520 base = &pvt->csels[umc].csbases[cs]; in read_umc_base_mask()
1521 base_sec = &pvt->csels[umc].csbases_sec[cs]; in read_umc_base_mask()
1528 umc, cs, *base, base_reg); in read_umc_base_mask()
1532 umc, cs, *base_sec, base_reg_sec); in read_umc_base_mask()
1535 umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK; in read_umc_base_mask()
1536 umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(UMCCH_ADDR_MASK_SEC); in read_umc_base_mask()
1538 for_each_chip_select_mask(cs, umc, pvt) { in read_umc_base_mask()
1539 mask = &pvt->csels[umc].csmasks[cs]; in read_umc_base_mask()
1540 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in read_umc_base_mask()
1547 umc, cs, *mask, mask_reg); in read_umc_base_mask()
1551 umc, cs, *mask_sec, mask_reg_sec); in read_umc_base_mask()
1565 if (pvt->umc) in read_dct_base_mask()
1609 struct amd64_umc *umc; in determine_memory_type_df() local
1613 umc = &pvt->umc[i]; in determine_memory_type_df()
1615 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) { in determine_memory_type_df()
1616 umc->dram_type = MEM_EMPTY; in determine_memory_type_df()
1624 if (fam_type->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) { in determine_memory_type_df()
1625 if (umc->dimm_cfg & BIT(5)) in determine_memory_type_df()
1626 umc->dram_type = MEM_LRDDR5; in determine_memory_type_df()
1627 else if (umc->dimm_cfg & BIT(4)) in determine_memory_type_df()
1628 umc->dram_type = MEM_RDDR5; in determine_memory_type_df()
1630 umc->dram_type = MEM_DDR5; in determine_memory_type_df()
1632 if (umc->dimm_cfg & BIT(5)) in determine_memory_type_df()
1633 umc->dram_type = MEM_LRDDR4; in determine_memory_type_df()
1634 else if (umc->dimm_cfg & BIT(4)) in determine_memory_type_df()
1635 umc->dram_type = MEM_RDDR4; in determine_memory_type_df()
1637 umc->dram_type = MEM_DDR4; in determine_memory_type_df()
1640 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]); in determine_memory_type_df()
1648 if (pvt->umc) in determine_memory_type()
2084 static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in f17_addr_mask_to_cs_size() argument
2129 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; in f17_addr_mask_to_cs_size()
2131 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; in f17_addr_mask_to_cs_size()
3182 if (pvt->umc) in reserve_mc_sibling_devs()
3214 if (pvt->umc) { in free_mc_sibling_devs()
3226 if (pvt->umc) { in determine_ecc_sym_sz()
3231 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in determine_ecc_sym_sz()
3232 if (pvt->umc[i].ecc_ctrl & BIT(9)) { in determine_ecc_sym_sz()
3235 } else if (pvt->umc[i].ecc_ctrl & BIT(7)) { in determine_ecc_sym_sz()
3261 struct amd64_umc *umc; in __read_mc_regs_df() local
3268 umc = &pvt->umc[i]; in __read_mc_regs_df()
3270 amd_smn_read(nid, umc_base + get_umc_reg(UMCCH_DIMM_CFG), &umc->dimm_cfg); in __read_mc_regs_df()
3271 amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); in __read_mc_regs_df()
3272 amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); in __read_mc_regs_df()
3273 amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); in __read_mc_regs_df()
3274 amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); in __read_mc_regs_df()
3303 if (pvt->umc) { in read_mc_regs()
3354 if (!pvt->umc) in read_mc_regs()
3400 if (!pvt->umc) { in get_csrow_nr_pages()
3424 u8 umc, cs; in init_csrows_df() local
3439 for_each_umc(umc) { in init_csrows_df()
3440 for_each_chip_select(cs, umc, pvt) { in init_csrows_df()
3441 if (!csrow_enabled(cs, umc, pvt)) in init_csrows_df()
3445 dimm = mci->csrows[cs]->channels[umc]->dimm; in init_csrows_df()
3450 dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); in init_csrows_df()
3451 dimm->mtype = pvt->umc[umc].dram_type; in init_csrows_df()
3475 if (pvt->umc) in init_csrows()
3707 struct amd64_umc *umc; in ecc_enabled() local
3710 umc = &pvt->umc[i]; in ecc_enabled()
3713 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) in ecc_enabled()
3718 if (umc->umc_cap_hi & UMC_ECC_ENABLED) in ecc_enabled()
3755 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in f17h_determine_edac_ctl_cap()
3756 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in f17h_determine_edac_ctl_cap()
3757 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in f17h_determine_edac_ctl_cap()
3759 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in f17h_determine_edac_ctl_cap()
3760 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in f17h_determine_edac_ctl_cap()
3787 if (pvt->umc) { in setup_mci_misc_attrs()
3935 pvt->umc = kcalloc(fam_type->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in hw_info_get()
3936 if (!pvt->umc) in hw_info_get()
3957 kfree(pvt->umc); in hw_info_put()