Lines Matching refs:dsp
278 bool (*validate_version)(struct cs_dsp *dsp, unsigned int version);
279 unsigned int (*parse_sizes)(struct cs_dsp *dsp,
283 int (*setup_algs)(struct cs_dsp *dsp);
287 void (*show_fw_status)(struct cs_dsp *dsp);
288 void (*stop_watchdog)(struct cs_dsp *dsp);
290 int (*enable_memory)(struct cs_dsp *dsp);
291 void (*disable_memory)(struct cs_dsp *dsp);
292 int (*lock_memory)(struct cs_dsp *dsp, unsigned int lock_regions);
294 int (*enable_core)(struct cs_dsp *dsp);
295 void (*disable_core)(struct cs_dsp *dsp);
297 int (*start_core)(struct cs_dsp *dsp);
298 void (*stop_core)(struct cs_dsp *dsp);
375 static void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, const char *s) in cs_dsp_debugfs_save_wmfwname() argument
379 kfree(dsp->wmfw_file_name); in cs_dsp_debugfs_save_wmfwname()
380 dsp->wmfw_file_name = tmp; in cs_dsp_debugfs_save_wmfwname()
383 static void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, const char *s) in cs_dsp_debugfs_save_binname() argument
387 kfree(dsp->bin_file_name); in cs_dsp_debugfs_save_binname()
388 dsp->bin_file_name = tmp; in cs_dsp_debugfs_save_binname()
391 static void cs_dsp_debugfs_clear(struct cs_dsp *dsp) in cs_dsp_debugfs_clear() argument
393 kfree(dsp->wmfw_file_name); in cs_dsp_debugfs_clear()
394 kfree(dsp->bin_file_name); in cs_dsp_debugfs_clear()
395 dsp->wmfw_file_name = NULL; in cs_dsp_debugfs_clear()
396 dsp->bin_file_name = NULL; in cs_dsp_debugfs_clear()
403 struct cs_dsp *dsp = file->private_data; in cs_dsp_debugfs_wmfw_read() local
406 mutex_lock(&dsp->pwr_lock); in cs_dsp_debugfs_wmfw_read()
408 if (!dsp->wmfw_file_name || !dsp->booted) in cs_dsp_debugfs_wmfw_read()
412 dsp->wmfw_file_name, in cs_dsp_debugfs_wmfw_read()
413 strlen(dsp->wmfw_file_name)); in cs_dsp_debugfs_wmfw_read()
415 mutex_unlock(&dsp->pwr_lock); in cs_dsp_debugfs_wmfw_read()
423 struct cs_dsp *dsp = file->private_data; in cs_dsp_debugfs_bin_read() local
426 mutex_lock(&dsp->pwr_lock); in cs_dsp_debugfs_bin_read()
428 if (!dsp->bin_file_name || !dsp->booted) in cs_dsp_debugfs_bin_read()
432 dsp->bin_file_name, in cs_dsp_debugfs_bin_read()
433 strlen(dsp->bin_file_name)); in cs_dsp_debugfs_bin_read()
435 mutex_unlock(&dsp->pwr_lock); in cs_dsp_debugfs_bin_read()
465 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) in cs_dsp_init_debugfs() argument
470 root = debugfs_create_dir(dsp->name, debugfs_root); in cs_dsp_init_debugfs()
472 debugfs_create_bool("booted", 0444, root, &dsp->booted); in cs_dsp_init_debugfs()
473 debugfs_create_bool("running", 0444, root, &dsp->running); in cs_dsp_init_debugfs()
474 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id); in cs_dsp_init_debugfs()
475 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version); in cs_dsp_init_debugfs()
479 dsp, &cs_dsp_debugfs_fops[i].fops); in cs_dsp_init_debugfs()
481 dsp->debugfs_root = root; in cs_dsp_init_debugfs()
489 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) in cs_dsp_cleanup_debugfs() argument
491 cs_dsp_debugfs_clear(dsp); in cs_dsp_cleanup_debugfs()
492 debugfs_remove_recursive(dsp->debugfs_root); in cs_dsp_cleanup_debugfs()
493 dsp->debugfs_root = NULL; in cs_dsp_cleanup_debugfs()
497 void cs_dsp_init_debugfs(struct cs_dsp *dsp, struct dentry *debugfs_root) in cs_dsp_init_debugfs() argument
502 void cs_dsp_cleanup_debugfs(struct cs_dsp *dsp) in cs_dsp_cleanup_debugfs() argument
507 static inline void cs_dsp_debugfs_save_wmfwname(struct cs_dsp *dsp, in cs_dsp_debugfs_save_wmfwname() argument
512 static inline void cs_dsp_debugfs_save_binname(struct cs_dsp *dsp, in cs_dsp_debugfs_save_binname() argument
517 static inline void cs_dsp_debugfs_clear(struct cs_dsp *dsp) in cs_dsp_debugfs_clear() argument
522 static const struct cs_dsp_region *cs_dsp_find_region(struct cs_dsp *dsp, in cs_dsp_find_region() argument
527 for (i = 0; i < dsp->num_mems; i++) in cs_dsp_find_region()
528 if (dsp->mem[i].type == type) in cs_dsp_find_region()
529 return &dsp->mem[i]; in cs_dsp_find_region()
569 static void cs_dsp_read_fw_status(struct cs_dsp *dsp, in cs_dsp_read_fw_status() argument
576 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]); in cs_dsp_read_fw_status()
578 cs_dsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); in cs_dsp_read_fw_status()
584 static void cs_dsp_adsp2_show_fw_status(struct cs_dsp *dsp) in cs_dsp_adsp2_show_fw_status() argument
590 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_adsp2_show_fw_status()
592 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_adsp2_show_fw_status()
596 static void cs_dsp_adsp2v2_show_fw_status(struct cs_dsp *dsp) in cs_dsp_adsp2v2_show_fw_status() argument
600 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_adsp2v2_show_fw_status()
602 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_adsp2v2_show_fw_status()
607 static void cs_dsp_halo_show_fw_status(struct cs_dsp *dsp) in cs_dsp_halo_show_fw_status() argument
613 cs_dsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); in cs_dsp_halo_show_fw_status()
615 cs_dsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", in cs_dsp_halo_show_fw_status()
623 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_base_reg() local
626 mem = cs_dsp_find_region(dsp, alg_region->type); in cs_dsp_coeff_base_reg()
628 cs_dsp_err(dsp, "No base for region %x\n", in cs_dsp_coeff_base_reg()
633 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset + off); in cs_dsp_coeff_base_reg()
652 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_write_acked_control() local
657 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_coeff_write_acked_control()
659 if (!dsp->running) in cs_dsp_coeff_write_acked_control()
666 cs_dsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", in cs_dsp_coeff_write_acked_control()
670 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_coeff_write_acked_control()
672 cs_dsp_err(dsp, "Failed to write %x: %d\n", reg, ret); in cs_dsp_coeff_write_acked_control()
694 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_coeff_write_acked_control()
696 cs_dsp_err(dsp, "Failed to read %x: %d\n", reg, ret); in cs_dsp_coeff_write_acked_control()
701 cs_dsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); in cs_dsp_coeff_write_acked_control()
706 cs_dsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", in cs_dsp_coeff_write_acked_control()
718 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_write_ctrl_raw() local
731 ret = regmap_raw_write(dsp->regmap, reg, scratch, in cs_dsp_coeff_write_ctrl_raw()
734 cs_dsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", in cs_dsp_coeff_write_ctrl_raw()
739 cs_dsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); in cs_dsp_coeff_write_ctrl_raw()
765 lockdep_assert_held(&ctl->dsp->pwr_lock); in cs_dsp_coeff_write_ctrl()
780 if (ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_write_ctrl()
793 struct cs_dsp *dsp = ctl->dsp; in cs_dsp_coeff_read_ctrl_raw() local
806 ret = regmap_raw_read(dsp->regmap, reg, scratch, len); in cs_dsp_coeff_read_ctrl_raw()
808 cs_dsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", in cs_dsp_coeff_read_ctrl_raw()
813 cs_dsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); in cs_dsp_coeff_read_ctrl_raw()
840 lockdep_assert_held(&ctl->dsp->pwr_lock); in cs_dsp_coeff_read_ctrl()
846 if (ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_read_ctrl()
851 if (!ctl->flags && ctl->enabled && ctl->dsp->running) in cs_dsp_coeff_read_ctrl()
862 static int cs_dsp_coeff_init_control_caches(struct cs_dsp *dsp) in cs_dsp_coeff_init_control_caches() argument
867 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_coeff_init_control_caches()
888 static int cs_dsp_coeff_sync_controls(struct cs_dsp *dsp) in cs_dsp_coeff_sync_controls() argument
893 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_coeff_sync_controls()
907 static void cs_dsp_signal_event_controls(struct cs_dsp *dsp, in cs_dsp_signal_event_controls() argument
913 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_signal_event_controls()
922 cs_dsp_warn(dsp, in cs_dsp_signal_event_controls()
935 static int cs_dsp_create_control(struct cs_dsp *dsp, in cs_dsp_create_control() argument
944 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_create_control()
945 if (ctl->fw_name == dsp->fw_name && in cs_dsp_create_control()
961 ctl->fw_name = dsp->fw_name; in cs_dsp_create_control()
963 if (subname && dsp->fw_ver >= 2) { in cs_dsp_create_control()
973 ctl->dsp = dsp; in cs_dsp_create_control()
985 list_add(&ctl->list, &dsp->ctl_list); in cs_dsp_create_control()
987 if (dsp->client_ops->control_add) { in cs_dsp_create_control()
988 ret = dsp->client_ops->control_add(ctl); in cs_dsp_create_control()
1066 static inline void cs_dsp_coeff_parse_alg(struct cs_dsp *dsp, const u8 **data, in cs_dsp_coeff_parse_alg() argument
1071 switch (dsp->fw_ver) { in cs_dsp_coeff_parse_alg()
1091 cs_dsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); in cs_dsp_coeff_parse_alg()
1092 cs_dsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); in cs_dsp_coeff_parse_alg()
1093 cs_dsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); in cs_dsp_coeff_parse_alg()
1096 static inline void cs_dsp_coeff_parse_coeff(struct cs_dsp *dsp, const u8 **data, in cs_dsp_coeff_parse_coeff() argument
1103 switch (dsp->fw_ver) { in cs_dsp_coeff_parse_coeff()
1134 cs_dsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); in cs_dsp_coeff_parse_coeff()
1135 cs_dsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); in cs_dsp_coeff_parse_coeff()
1136 cs_dsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); in cs_dsp_coeff_parse_coeff()
1137 cs_dsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); in cs_dsp_coeff_parse_coeff()
1138 cs_dsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); in cs_dsp_coeff_parse_coeff()
1139 cs_dsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); in cs_dsp_coeff_parse_coeff()
1142 static int cs_dsp_check_coeff_flags(struct cs_dsp *dsp, in cs_dsp_check_coeff_flags() argument
1149 cs_dsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", in cs_dsp_check_coeff_flags()
1157 static int cs_dsp_parse_coeff(struct cs_dsp *dsp, in cs_dsp_parse_coeff() argument
1166 cs_dsp_coeff_parse_alg(dsp, &data, &alg_blk); in cs_dsp_parse_coeff()
1168 cs_dsp_coeff_parse_coeff(dsp, &data, &coeff_blk); in cs_dsp_parse_coeff()
1177 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1187 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1197 ret = cs_dsp_check_coeff_flags(dsp, &coeff_blk, in cs_dsp_parse_coeff()
1206 cs_dsp_err(dsp, "Unknown control type: %d\n", in cs_dsp_parse_coeff()
1214 ret = cs_dsp_create_control(dsp, &alg_region, in cs_dsp_parse_coeff()
1222 cs_dsp_err(dsp, "Failed to create control: %.*s, %d\n", in cs_dsp_parse_coeff()
1229 static unsigned int cs_dsp_adsp1_parse_sizes(struct cs_dsp *dsp, in cs_dsp_adsp1_parse_sizes() argument
1238 cs_dsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, in cs_dsp_adsp1_parse_sizes()
1245 static unsigned int cs_dsp_adsp2_parse_sizes(struct cs_dsp *dsp, in cs_dsp_adsp2_parse_sizes() argument
1254 cs_dsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, in cs_dsp_adsp2_parse_sizes()
1261 static bool cs_dsp_validate_version(struct cs_dsp *dsp, unsigned int version) in cs_dsp_validate_version() argument
1265 cs_dsp_warn(dsp, "Deprecated file format %d\n", version); in cs_dsp_validate_version()
1275 static bool cs_dsp_halo_validate_version(struct cs_dsp *dsp, unsigned int version) in cs_dsp_halo_validate_version() argument
1285 static int cs_dsp_load(struct cs_dsp *dsp, const struct firmware *firmware, in cs_dsp_load() argument
1289 struct regmap *regmap = dsp->regmap; in cs_dsp_load()
1307 cs_dsp_err(dsp, "%s: file too short, %zu bytes\n", in cs_dsp_load()
1315 cs_dsp_err(dsp, "%s: invalid magic\n", file); in cs_dsp_load()
1319 if (!dsp->ops->validate_version(dsp, header->ver)) { in cs_dsp_load()
1320 cs_dsp_err(dsp, "%s: unknown file format %d\n", in cs_dsp_load()
1325 cs_dsp_info(dsp, "Firmware version: %d\n", header->ver); in cs_dsp_load()
1326 dsp->fw_ver = header->ver; in cs_dsp_load()
1328 if (header->core != dsp->type) { in cs_dsp_load()
1329 cs_dsp_err(dsp, "%s: invalid core %d != %d\n", in cs_dsp_load()
1330 file, header->core, dsp->type); in cs_dsp_load()
1335 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware); in cs_dsp_load()
1341 cs_dsp_err(dsp, "%s: unexpected header length %d\n", in cs_dsp_load()
1346 cs_dsp_dbg(dsp, "%s: timestamp %llu\n", file, in cs_dsp_load()
1366 ret = cs_dsp_parse_coeff(dsp, region); in cs_dsp_load()
1387 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load()
1389 cs_dsp_err(dsp, "No region of type: %x\n", type); in cs_dsp_load()
1395 reg = dsp->ops->region_to_reg(mem, offset); in cs_dsp_load()
1398 cs_dsp_warn(dsp, in cs_dsp_load()
1404 cs_dsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, in cs_dsp_load()
1410 cs_dsp_err(dsp, in cs_dsp_load()
1420 cs_dsp_info(dsp, "%s: %s\n", file, text); in cs_dsp_load()
1430 cs_dsp_err(dsp, "Out of memory\n"); in cs_dsp_load()
1438 cs_dsp_err(dsp, in cs_dsp_load()
1453 cs_dsp_err(dsp, "Failed to complete async write: %d\n", ret); in cs_dsp_load()
1458 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", in cs_dsp_load()
1461 cs_dsp_debugfs_save_wmfwname(dsp, file); in cs_dsp_load()
1482 struct cs_dsp_coeff_ctl *cs_dsp_get_ctl(struct cs_dsp *dsp, const char *name, int type, in cs_dsp_get_ctl() argument
1487 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_get_ctl()
1489 list_for_each_entry(pos, &dsp->ctl_list, list) { in cs_dsp_get_ctl()
1493 pos->fw_name == dsp->fw_name && in cs_dsp_get_ctl()
1505 static void cs_dsp_ctl_fixup_base(struct cs_dsp *dsp, in cs_dsp_ctl_fixup_base() argument
1510 list_for_each_entry(ctl, &dsp->ctl_list, list) { in cs_dsp_ctl_fixup_base()
1511 if (ctl->fw_name == dsp->fw_name && in cs_dsp_ctl_fixup_base()
1519 static void *cs_dsp_read_algs(struct cs_dsp *dsp, size_t n_algs, in cs_dsp_read_algs() argument
1529 cs_dsp_err(dsp, "No algorithms\n"); in cs_dsp_read_algs()
1534 cs_dsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); in cs_dsp_read_algs()
1539 reg = dsp->ops->region_to_reg(mem, pos + len); in cs_dsp_read_algs()
1541 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_read_algs()
1543 cs_dsp_err(dsp, "Failed to read algorithm list end: %d\n", in cs_dsp_read_algs()
1549 cs_dsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", in cs_dsp_read_algs()
1559 reg = dsp->ops->region_to_reg(mem, pos); in cs_dsp_read_algs()
1561 ret = regmap_raw_read(dsp->regmap, reg, alg, len); in cs_dsp_read_algs()
1563 cs_dsp_err(dsp, "Failed to read algorithm list: %d\n", ret); in cs_dsp_read_algs()
1579 struct cs_dsp_alg_region *cs_dsp_find_alg_region(struct cs_dsp *dsp, in cs_dsp_find_alg_region() argument
1584 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_find_alg_region()
1586 list_for_each_entry(alg_region, &dsp->alg_regions, list) { in cs_dsp_find_alg_region()
1595 static struct cs_dsp_alg_region *cs_dsp_create_region(struct cs_dsp *dsp, in cs_dsp_create_region() argument
1610 list_add_tail(&alg_region->list, &dsp->alg_regions); in cs_dsp_create_region()
1612 if (dsp->fw_ver > 0) in cs_dsp_create_region()
1613 cs_dsp_ctl_fixup_base(dsp, alg_region); in cs_dsp_create_region()
1618 static void cs_dsp_free_alg_regions(struct cs_dsp *dsp) in cs_dsp_free_alg_regions() argument
1622 while (!list_empty(&dsp->alg_regions)) { in cs_dsp_free_alg_regions()
1623 alg_region = list_first_entry(&dsp->alg_regions, in cs_dsp_free_alg_regions()
1631 static void cs_dsp_parse_wmfw_id_header(struct cs_dsp *dsp, in cs_dsp_parse_wmfw_id_header() argument
1634 dsp->fw_id = be32_to_cpu(fw->id); in cs_dsp_parse_wmfw_id_header()
1635 dsp->fw_id_version = be32_to_cpu(fw->ver); in cs_dsp_parse_wmfw_id_header()
1637 cs_dsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n", in cs_dsp_parse_wmfw_id_header()
1638 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, in cs_dsp_parse_wmfw_id_header()
1639 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, in cs_dsp_parse_wmfw_id_header()
1643 static void cs_dsp_parse_wmfw_v3_id_header(struct cs_dsp *dsp, in cs_dsp_parse_wmfw_v3_id_header() argument
1646 dsp->fw_id = be32_to_cpu(fw->id); in cs_dsp_parse_wmfw_v3_id_header()
1647 dsp->fw_id_version = be32_to_cpu(fw->ver); in cs_dsp_parse_wmfw_v3_id_header()
1648 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id); in cs_dsp_parse_wmfw_v3_id_header()
1650 cs_dsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n", in cs_dsp_parse_wmfw_v3_id_header()
1651 dsp->fw_id, dsp->fw_vendor_id, in cs_dsp_parse_wmfw_v3_id_header()
1652 (dsp->fw_id_version & 0xff0000) >> 16, in cs_dsp_parse_wmfw_v3_id_header()
1653 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, in cs_dsp_parse_wmfw_v3_id_header()
1657 static int cs_dsp_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, in cs_dsp_create_regions() argument
1664 alg_region = cs_dsp_create_region(dsp, type[i], id, ver, base[i]); in cs_dsp_create_regions()
1672 static int cs_dsp_adsp1_setup_algs(struct cs_dsp *dsp) in cs_dsp_adsp1_setup_algs() argument
1682 mem = cs_dsp_find_region(dsp, WMFW_ADSP1_DM); in cs_dsp_adsp1_setup_algs()
1686 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, in cs_dsp_adsp1_setup_algs()
1689 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_adsp1_setup_algs()
1696 cs_dsp_parse_wmfw_id_header(dsp, &adsp1_id.fw, n_algs); in cs_dsp_adsp1_setup_algs()
1698 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, in cs_dsp_adsp1_setup_algs()
1704 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, in cs_dsp_adsp1_setup_algs()
1714 adsp1_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_adsp1_setup_algs()
1719 cs_dsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", in cs_dsp_adsp1_setup_algs()
1727 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_DM, in cs_dsp_adsp1_setup_algs()
1735 if (dsp->fw_ver == 0) { in cs_dsp_adsp1_setup_algs()
1740 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp1_setup_algs()
1744 cs_dsp_warn(dsp, "Missing length info for region DM with ID %x\n", in cs_dsp_adsp1_setup_algs()
1749 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP1_ZM, in cs_dsp_adsp1_setup_algs()
1757 if (dsp->fw_ver == 0) { in cs_dsp_adsp1_setup_algs()
1762 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp1_setup_algs()
1766 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", in cs_dsp_adsp1_setup_algs()
1777 static int cs_dsp_adsp2_setup_algs(struct cs_dsp *dsp) in cs_dsp_adsp2_setup_algs() argument
1787 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); in cs_dsp_adsp2_setup_algs()
1791 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, in cs_dsp_adsp2_setup_algs()
1794 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_adsp2_setup_algs()
1801 cs_dsp_parse_wmfw_id_header(dsp, &adsp2_id.fw, n_algs); in cs_dsp_adsp2_setup_algs()
1803 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, in cs_dsp_adsp2_setup_algs()
1809 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, in cs_dsp_adsp2_setup_algs()
1815 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, in cs_dsp_adsp2_setup_algs()
1825 adsp2_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_adsp2_setup_algs()
1830 cs_dsp_info(dsp, in cs_dsp_adsp2_setup_algs()
1840 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_XM, in cs_dsp_adsp2_setup_algs()
1848 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
1853 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
1857 cs_dsp_warn(dsp, "Missing length info for region XM with ID %x\n", in cs_dsp_adsp2_setup_algs()
1862 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_YM, in cs_dsp_adsp2_setup_algs()
1870 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
1875 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
1879 cs_dsp_warn(dsp, "Missing length info for region YM with ID %x\n", in cs_dsp_adsp2_setup_algs()
1884 alg_region = cs_dsp_create_region(dsp, WMFW_ADSP2_ZM, in cs_dsp_adsp2_setup_algs()
1892 if (dsp->fw_ver == 0) { in cs_dsp_adsp2_setup_algs()
1897 cs_dsp_create_control(dsp, alg_region, 0, in cs_dsp_adsp2_setup_algs()
1901 cs_dsp_warn(dsp, "Missing length info for region ZM with ID %x\n", in cs_dsp_adsp2_setup_algs()
1912 static int cs_dsp_halo_create_regions(struct cs_dsp *dsp, __be32 id, __be32 ver, in cs_dsp_halo_create_regions() argument
1921 return cs_dsp_create_regions(dsp, id, ver, ARRAY_SIZE(types), types, bases); in cs_dsp_halo_create_regions()
1924 static int cs_dsp_halo_setup_algs(struct cs_dsp *dsp) in cs_dsp_halo_setup_algs() argument
1933 mem = cs_dsp_find_region(dsp, WMFW_ADSP2_XM); in cs_dsp_halo_setup_algs()
1937 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, in cs_dsp_halo_setup_algs()
1940 cs_dsp_err(dsp, "Failed to read algorithm info: %d\n", in cs_dsp_halo_setup_algs()
1947 cs_dsp_parse_wmfw_v3_id_header(dsp, &halo_id.fw, n_algs); in cs_dsp_halo_setup_algs()
1949 ret = cs_dsp_halo_create_regions(dsp, halo_id.fw.id, halo_id.fw.ver, in cs_dsp_halo_setup_algs()
1958 halo_alg = cs_dsp_read_algs(dsp, n_algs, mem, pos, len); in cs_dsp_halo_setup_algs()
1963 cs_dsp_info(dsp, in cs_dsp_halo_setup_algs()
1972 ret = cs_dsp_halo_create_regions(dsp, halo_alg[i].alg.id, in cs_dsp_halo_setup_algs()
1985 static int cs_dsp_load_coeff(struct cs_dsp *dsp, const struct firmware *firmware, in cs_dsp_load_coeff() argument
1989 struct regmap *regmap = dsp->regmap; in cs_dsp_load_coeff()
2005 cs_dsp_err(dsp, "%s: coefficient file too short, %zu bytes\n", in cs_dsp_load_coeff()
2012 cs_dsp_err(dsp, "%s: invalid coefficient magic\n", file); in cs_dsp_load_coeff()
2021 cs_dsp_err(dsp, "%s: Unsupported coefficient file format %d\n", in cs_dsp_load_coeff()
2027 cs_dsp_dbg(dsp, "%s: v%d.%d.%d\n", file, in cs_dsp_load_coeff()
2043 cs_dsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", in cs_dsp_load_coeff()
2048 cs_dsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", in cs_dsp_load_coeff()
2065 if (le32_to_cpu(blk->id) == dsp->fw_id && in cs_dsp_load_coeff()
2068 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load_coeff()
2070 cs_dsp_err(dsp, "No ZM\n"); in cs_dsp_load_coeff()
2073 reg = dsp->ops->region_to_reg(mem, 0); in cs_dsp_load_coeff()
2088 cs_dsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", in cs_dsp_load_coeff()
2092 mem = cs_dsp_find_region(dsp, type); in cs_dsp_load_coeff()
2094 cs_dsp_err(dsp, "No base for region %x\n", type); in cs_dsp_load_coeff()
2098 alg_region = cs_dsp_find_alg_region(dsp, type, in cs_dsp_load_coeff()
2102 cs_dsp_warn(dsp, in cs_dsp_load_coeff()
2112 reg = dsp->ops->region_to_reg(mem, reg); in cs_dsp_load_coeff()
2115 cs_dsp_err(dsp, "No %x for algorithm %x\n", in cs_dsp_load_coeff()
2121 cs_dsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", in cs_dsp_load_coeff()
2128 cs_dsp_info(dsp, "%s: %s\n", dsp->fw_name, text); in cs_dsp_load_coeff()
2136 cs_dsp_err(dsp, in cs_dsp_load_coeff()
2149 cs_dsp_err(dsp, "Out of memory\n"); in cs_dsp_load_coeff()
2154 cs_dsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", in cs_dsp_load_coeff()
2160 cs_dsp_err(dsp, in cs_dsp_load_coeff()
2172 cs_dsp_err(dsp, "Failed to complete async write: %d\n", ret); in cs_dsp_load_coeff()
2175 cs_dsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", in cs_dsp_load_coeff()
2178 cs_dsp_debugfs_save_binname(dsp, file); in cs_dsp_load_coeff()
2187 static int cs_dsp_create_name(struct cs_dsp *dsp) in cs_dsp_create_name() argument
2189 if (!dsp->name) { in cs_dsp_create_name()
2190 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", in cs_dsp_create_name()
2191 dsp->num); in cs_dsp_create_name()
2192 if (!dsp->name) in cs_dsp_create_name()
2199 static int cs_dsp_common_init(struct cs_dsp *dsp) in cs_dsp_common_init() argument
2203 ret = cs_dsp_create_name(dsp); in cs_dsp_common_init()
2207 INIT_LIST_HEAD(&dsp->alg_regions); in cs_dsp_common_init()
2208 INIT_LIST_HEAD(&dsp->ctl_list); in cs_dsp_common_init()
2210 mutex_init(&dsp->pwr_lock); in cs_dsp_common_init()
2221 int cs_dsp_adsp1_init(struct cs_dsp *dsp) in cs_dsp_adsp1_init() argument
2223 dsp->ops = &cs_dsp_adsp1_ops; in cs_dsp_adsp1_init()
2225 return cs_dsp_common_init(dsp); in cs_dsp_adsp1_init()
2240 int cs_dsp_adsp1_power_up(struct cs_dsp *dsp, in cs_dsp_adsp1_power_up() argument
2248 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2250 dsp->fw_name = fw_name; in cs_dsp_adsp1_power_up()
2252 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2259 if (dsp->sysclk_reg) { in cs_dsp_adsp1_power_up()
2260 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); in cs_dsp_adsp1_power_up()
2262 cs_dsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret); in cs_dsp_adsp1_power_up()
2266 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; in cs_dsp_adsp1_power_up()
2268 ret = regmap_update_bits(dsp->regmap, in cs_dsp_adsp1_power_up()
2269 dsp->base + ADSP1_CONTROL_31, in cs_dsp_adsp1_power_up()
2272 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); in cs_dsp_adsp1_power_up()
2277 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); in cs_dsp_adsp1_power_up()
2281 ret = cs_dsp_adsp1_setup_algs(dsp); in cs_dsp_adsp1_power_up()
2285 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); in cs_dsp_adsp1_power_up()
2290 ret = cs_dsp_coeff_init_control_caches(dsp); in cs_dsp_adsp1_power_up()
2295 ret = cs_dsp_coeff_sync_controls(dsp); in cs_dsp_adsp1_power_up()
2299 dsp->booted = true; in cs_dsp_adsp1_power_up()
2302 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2306 dsp->running = true; in cs_dsp_adsp1_power_up()
2308 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2313 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_up()
2316 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_up()
2325 void cs_dsp_adsp1_power_down(struct cs_dsp *dsp) in cs_dsp_adsp1_power_down() argument
2329 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp1_power_down()
2331 dsp->running = false; in cs_dsp_adsp1_power_down()
2332 dsp->booted = false; in cs_dsp_adsp1_power_down()
2335 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_down()
2338 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, in cs_dsp_adsp1_power_down()
2341 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, in cs_dsp_adsp1_power_down()
2344 list_for_each_entry(ctl, &dsp->ctl_list, list) in cs_dsp_adsp1_power_down()
2347 cs_dsp_free_alg_regions(dsp); in cs_dsp_adsp1_power_down()
2349 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp1_power_down()
2353 static int cs_dsp_adsp2v2_enable_core(struct cs_dsp *dsp) in cs_dsp_adsp2v2_enable_core() argument
2360 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); in cs_dsp_adsp2v2_enable_core()
2371 cs_dsp_err(dsp, "Failed to start DSP RAM\n"); in cs_dsp_adsp2v2_enable_core()
2375 cs_dsp_dbg(dsp, "RAM ready after %d polls\n", count); in cs_dsp_adsp2v2_enable_core()
2380 static int cs_dsp_adsp2_enable_core(struct cs_dsp *dsp) in cs_dsp_adsp2_enable_core() argument
2384 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_enable_core()
2389 return cs_dsp_adsp2v2_enable_core(dsp); in cs_dsp_adsp2_enable_core()
2392 static int cs_dsp_adsp2_lock(struct cs_dsp *dsp, unsigned int lock_regions) in cs_dsp_adsp2_lock() argument
2394 struct regmap *regmap = dsp->regmap; in cs_dsp_adsp2_lock()
2401 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; in cs_dsp_adsp2_lock()
2422 static int cs_dsp_adsp2_enable_memory(struct cs_dsp *dsp) in cs_dsp_adsp2_enable_memory() argument
2424 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_enable_memory()
2428 static void cs_dsp_adsp2_disable_memory(struct cs_dsp *dsp) in cs_dsp_adsp2_disable_memory() argument
2430 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_disable_memory()
2434 static void cs_dsp_adsp2_disable_core(struct cs_dsp *dsp) in cs_dsp_adsp2_disable_core() argument
2436 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); in cs_dsp_adsp2_disable_core()
2437 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); in cs_dsp_adsp2_disable_core()
2438 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); in cs_dsp_adsp2_disable_core()
2440 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_disable_core()
2444 static void cs_dsp_adsp2v2_disable_core(struct cs_dsp *dsp) in cs_dsp_adsp2v2_disable_core() argument
2446 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); in cs_dsp_adsp2v2_disable_core()
2447 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); in cs_dsp_adsp2v2_disable_core()
2448 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); in cs_dsp_adsp2v2_disable_core()
2451 static int cs_dsp_halo_configure_mpu(struct cs_dsp *dsp, unsigned int lock_regions) in cs_dsp_halo_configure_mpu() argument
2454 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, in cs_dsp_halo_configure_mpu()
2455 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, in cs_dsp_halo_configure_mpu()
2456 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2457 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2458 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2459 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2460 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, in cs_dsp_halo_configure_mpu()
2461 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2462 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2463 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2464 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2465 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, in cs_dsp_halo_configure_mpu()
2466 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2467 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2468 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2469 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2470 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, in cs_dsp_halo_configure_mpu()
2471 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2472 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, in cs_dsp_halo_configure_mpu()
2473 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2474 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2475 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, in cs_dsp_halo_configure_mpu()
2476 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, in cs_dsp_halo_configure_mpu()
2479 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config)); in cs_dsp_halo_configure_mpu()
2491 int cs_dsp_set_dspclk(struct cs_dsp *dsp, unsigned int freq) in cs_dsp_set_dspclk() argument
2495 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, in cs_dsp_set_dspclk()
2499 cs_dsp_err(dsp, "Failed to set clock rate: %d\n", ret); in cs_dsp_set_dspclk()
2505 static void cs_dsp_stop_watchdog(struct cs_dsp *dsp) in cs_dsp_stop_watchdog() argument
2507 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, in cs_dsp_stop_watchdog()
2511 static void cs_dsp_halo_stop_watchdog(struct cs_dsp *dsp) in cs_dsp_halo_stop_watchdog() argument
2513 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, in cs_dsp_halo_stop_watchdog()
2534 int cs_dsp_power_up(struct cs_dsp *dsp, in cs_dsp_power_up() argument
2541 mutex_lock(&dsp->pwr_lock); in cs_dsp_power_up()
2543 dsp->fw_name = fw_name; in cs_dsp_power_up()
2545 if (dsp->ops->enable_memory) { in cs_dsp_power_up()
2546 ret = dsp->ops->enable_memory(dsp); in cs_dsp_power_up()
2551 if (dsp->ops->enable_core) { in cs_dsp_power_up()
2552 ret = dsp->ops->enable_core(dsp); in cs_dsp_power_up()
2557 ret = cs_dsp_load(dsp, wmfw_firmware, wmfw_filename); in cs_dsp_power_up()
2561 ret = dsp->ops->setup_algs(dsp); in cs_dsp_power_up()
2565 ret = cs_dsp_load_coeff(dsp, coeff_firmware, coeff_filename); in cs_dsp_power_up()
2570 ret = cs_dsp_coeff_init_control_caches(dsp); in cs_dsp_power_up()
2574 if (dsp->ops->disable_core) in cs_dsp_power_up()
2575 dsp->ops->disable_core(dsp); in cs_dsp_power_up()
2577 dsp->booted = true; in cs_dsp_power_up()
2579 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_up()
2583 if (dsp->ops->disable_core) in cs_dsp_power_up()
2584 dsp->ops->disable_core(dsp); in cs_dsp_power_up()
2586 if (dsp->ops->disable_memory) in cs_dsp_power_up()
2587 dsp->ops->disable_memory(dsp); in cs_dsp_power_up()
2589 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_up()
2602 void cs_dsp_power_down(struct cs_dsp *dsp) in cs_dsp_power_down() argument
2606 mutex_lock(&dsp->pwr_lock); in cs_dsp_power_down()
2608 cs_dsp_debugfs_clear(dsp); in cs_dsp_power_down()
2610 dsp->fw_id = 0; in cs_dsp_power_down()
2611 dsp->fw_id_version = 0; in cs_dsp_power_down()
2613 dsp->booted = false; in cs_dsp_power_down()
2615 if (dsp->ops->disable_memory) in cs_dsp_power_down()
2616 dsp->ops->disable_memory(dsp); in cs_dsp_power_down()
2618 list_for_each_entry(ctl, &dsp->ctl_list, list) in cs_dsp_power_down()
2621 cs_dsp_free_alg_regions(dsp); in cs_dsp_power_down()
2623 mutex_unlock(&dsp->pwr_lock); in cs_dsp_power_down()
2625 cs_dsp_dbg(dsp, "Shutdown complete\n"); in cs_dsp_power_down()
2629 static int cs_dsp_adsp2_start_core(struct cs_dsp *dsp) in cs_dsp_adsp2_start_core() argument
2631 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_start_core()
2636 static void cs_dsp_adsp2_stop_core(struct cs_dsp *dsp) in cs_dsp_adsp2_stop_core() argument
2638 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_stop_core()
2650 int cs_dsp_run(struct cs_dsp *dsp) in cs_dsp_run() argument
2654 mutex_lock(&dsp->pwr_lock); in cs_dsp_run()
2656 if (!dsp->booted) { in cs_dsp_run()
2661 if (dsp->ops->enable_core) { in cs_dsp_run()
2662 ret = dsp->ops->enable_core(dsp); in cs_dsp_run()
2667 if (dsp->client_ops->pre_run) { in cs_dsp_run()
2668 ret = dsp->client_ops->pre_run(dsp); in cs_dsp_run()
2674 ret = cs_dsp_coeff_sync_controls(dsp); in cs_dsp_run()
2678 if (dsp->ops->lock_memory) { in cs_dsp_run()
2679 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions); in cs_dsp_run()
2681 cs_dsp_err(dsp, "Error configuring MPU: %d\n", ret); in cs_dsp_run()
2686 if (dsp->ops->start_core) { in cs_dsp_run()
2687 ret = dsp->ops->start_core(dsp); in cs_dsp_run()
2692 dsp->running = true; in cs_dsp_run()
2694 if (dsp->client_ops->post_run) { in cs_dsp_run()
2695 ret = dsp->client_ops->post_run(dsp); in cs_dsp_run()
2700 mutex_unlock(&dsp->pwr_lock); in cs_dsp_run()
2705 if (dsp->ops->stop_core) in cs_dsp_run()
2706 dsp->ops->stop_core(dsp); in cs_dsp_run()
2707 if (dsp->ops->disable_core) in cs_dsp_run()
2708 dsp->ops->disable_core(dsp); in cs_dsp_run()
2709 mutex_unlock(&dsp->pwr_lock); in cs_dsp_run()
2721 void cs_dsp_stop(struct cs_dsp *dsp) in cs_dsp_stop() argument
2724 cs_dsp_signal_event_controls(dsp, CS_DSP_FW_EVENT_SHUTDOWN); in cs_dsp_stop()
2726 if (dsp->ops->stop_watchdog) in cs_dsp_stop()
2727 dsp->ops->stop_watchdog(dsp); in cs_dsp_stop()
2730 if (dsp->ops->show_fw_status) in cs_dsp_stop()
2731 dsp->ops->show_fw_status(dsp); in cs_dsp_stop()
2733 mutex_lock(&dsp->pwr_lock); in cs_dsp_stop()
2735 if (dsp->client_ops->pre_stop) in cs_dsp_stop()
2736 dsp->client_ops->pre_stop(dsp); in cs_dsp_stop()
2738 dsp->running = false; in cs_dsp_stop()
2740 if (dsp->ops->stop_core) in cs_dsp_stop()
2741 dsp->ops->stop_core(dsp); in cs_dsp_stop()
2742 if (dsp->ops->disable_core) in cs_dsp_stop()
2743 dsp->ops->disable_core(dsp); in cs_dsp_stop()
2745 if (dsp->client_ops->post_stop) in cs_dsp_stop()
2746 dsp->client_ops->post_stop(dsp); in cs_dsp_stop()
2748 mutex_unlock(&dsp->pwr_lock); in cs_dsp_stop()
2750 cs_dsp_dbg(dsp, "Execution stopped\n"); in cs_dsp_stop()
2754 static int cs_dsp_halo_start_core(struct cs_dsp *dsp) in cs_dsp_halo_start_core() argument
2758 ret = regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_start_core()
2764 return regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_start_core()
2768 static void cs_dsp_halo_stop_core(struct cs_dsp *dsp) in cs_dsp_halo_stop_core() argument
2770 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, in cs_dsp_halo_stop_core()
2774 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, in cs_dsp_halo_stop_core()
2784 int cs_dsp_adsp2_init(struct cs_dsp *dsp) in cs_dsp_adsp2_init() argument
2788 switch (dsp->rev) { in cs_dsp_adsp2_init()
2794 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, in cs_dsp_adsp2_init()
2797 cs_dsp_err(dsp, in cs_dsp_adsp2_init()
2802 dsp->ops = &cs_dsp_adsp2_ops[0]; in cs_dsp_adsp2_init()
2805 dsp->ops = &cs_dsp_adsp2_ops[1]; in cs_dsp_adsp2_init()
2808 dsp->ops = &cs_dsp_adsp2_ops[2]; in cs_dsp_adsp2_init()
2812 return cs_dsp_common_init(dsp); in cs_dsp_adsp2_init()
2822 int cs_dsp_halo_init(struct cs_dsp *dsp) in cs_dsp_halo_init() argument
2824 dsp->ops = &cs_dsp_halo_ops; in cs_dsp_halo_init()
2826 return cs_dsp_common_init(dsp); in cs_dsp_halo_init()
2834 void cs_dsp_remove(struct cs_dsp *dsp) in cs_dsp_remove() argument
2838 while (!list_empty(&dsp->ctl_list)) { in cs_dsp_remove()
2839 ctl = list_first_entry(&dsp->ctl_list, struct cs_dsp_coeff_ctl, list); in cs_dsp_remove()
2841 if (dsp->client_ops->control_remove) in cs_dsp_remove()
2842 dsp->client_ops->control_remove(ctl); in cs_dsp_remove()
2864 int cs_dsp_read_raw_data_block(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, in cs_dsp_read_raw_data_block() argument
2867 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); in cs_dsp_read_raw_data_block()
2871 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_read_raw_data_block()
2876 reg = dsp->ops->region_to_reg(mem, mem_addr); in cs_dsp_read_raw_data_block()
2878 ret = regmap_raw_read(dsp->regmap, reg, data, in cs_dsp_read_raw_data_block()
2896 int cs_dsp_read_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 *data) in cs_dsp_read_data_word() argument
2901 ret = cs_dsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw); in cs_dsp_read_data_word()
2920 int cs_dsp_write_data_word(struct cs_dsp *dsp, int mem_type, unsigned int mem_addr, u32 data) in cs_dsp_write_data_word() argument
2922 struct cs_dsp_region const *mem = cs_dsp_find_region(dsp, mem_type); in cs_dsp_write_data_word()
2926 lockdep_assert_held(&dsp->pwr_lock); in cs_dsp_write_data_word()
2931 reg = dsp->ops->region_to_reg(mem, mem_addr); in cs_dsp_write_data_word()
2933 return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); in cs_dsp_write_data_word()
2967 void cs_dsp_adsp2_bus_error(struct cs_dsp *dsp) in cs_dsp_adsp2_bus_error() argument
2970 struct regmap *regmap = dsp->regmap; in cs_dsp_adsp2_bus_error()
2973 mutex_lock(&dsp->pwr_lock); in cs_dsp_adsp2_bus_error()
2975 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); in cs_dsp_adsp2_bus_error()
2977 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
2983 cs_dsp_err(dsp, "watchdog timeout error\n"); in cs_dsp_adsp2_bus_error()
2984 dsp->ops->stop_watchdog(dsp); in cs_dsp_adsp2_bus_error()
2985 if (dsp->client_ops->watchdog_expired) in cs_dsp_adsp2_bus_error()
2986 dsp->client_ops->watchdog_expired(dsp); in cs_dsp_adsp2_bus_error()
2991 cs_dsp_err(dsp, "bus error: address error\n"); in cs_dsp_adsp2_bus_error()
2993 cs_dsp_err(dsp, "bus error: region lock error\n"); in cs_dsp_adsp2_bus_error()
2995 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); in cs_dsp_adsp2_bus_error()
2997 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
3003 cs_dsp_err(dsp, "bus error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3007 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, in cs_dsp_adsp2_bus_error()
3010 cs_dsp_err(dsp, in cs_dsp_adsp2_bus_error()
3016 cs_dsp_err(dsp, "xmem error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3018 cs_dsp_err(dsp, "pmem error address = 0x%x\n", in cs_dsp_adsp2_bus_error()
3023 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, in cs_dsp_adsp2_bus_error()
3027 mutex_unlock(&dsp->pwr_lock); in cs_dsp_adsp2_bus_error()
3037 void cs_dsp_halo_bus_error(struct cs_dsp *dsp) in cs_dsp_halo_bus_error() argument
3039 struct regmap *regmap = dsp->regmap; in cs_dsp_halo_bus_error()
3042 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3043 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3044 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, in cs_dsp_halo_bus_error()
3048 mutex_lock(&dsp->pwr_lock); in cs_dsp_halo_bus_error()
3050 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, in cs_dsp_halo_bus_error()
3053 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret); in cs_dsp_halo_bus_error()
3057 cs_dsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n", in cs_dsp_halo_bus_error()
3062 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, in cs_dsp_halo_bus_error()
3065 cs_dsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret); in cs_dsp_halo_bus_error()
3069 cs_dsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault); in cs_dsp_halo_bus_error()
3071 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, in cs_dsp_halo_bus_error()
3074 cs_dsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret); in cs_dsp_halo_bus_error()
3078 cs_dsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]); in cs_dsp_halo_bus_error()
3079 cs_dsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]); in cs_dsp_halo_bus_error()
3080 cs_dsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]); in cs_dsp_halo_bus_error()
3082 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear)); in cs_dsp_halo_bus_error()
3084 cs_dsp_warn(dsp, "Failed to clear MPU status: %d\n", ret); in cs_dsp_halo_bus_error()
3087 mutex_unlock(&dsp->pwr_lock); in cs_dsp_halo_bus_error()
3097 void cs_dsp_halo_wdt_expire(struct cs_dsp *dsp) in cs_dsp_halo_wdt_expire() argument
3099 mutex_lock(&dsp->pwr_lock); in cs_dsp_halo_wdt_expire()
3101 cs_dsp_warn(dsp, "WDT Expiry Fault\n"); in cs_dsp_halo_wdt_expire()
3103 dsp->ops->stop_watchdog(dsp); in cs_dsp_halo_wdt_expire()
3104 if (dsp->client_ops->watchdog_expired) in cs_dsp_halo_wdt_expire()
3105 dsp->client_ops->watchdog_expired(dsp); in cs_dsp_halo_wdt_expire()
3107 mutex_unlock(&dsp->pwr_lock); in cs_dsp_halo_wdt_expire()