Lines Matching refs:gc
39 struct gpio_chip gc; member
64 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc) in brcmstb_gpio_gc_to_priv() argument
66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv()
75 return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & in __brcmstb_gpio_get_active_irqs()
76 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)); in __brcmstb_gpio_get_active_irqs()
85 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
87 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_get_active_irqs()
95 return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); in brcmstb_gpio_hwirq_to_offset()
101 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_set_imask() local
107 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); in brcmstb_gpio_set_imask()
108 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); in brcmstb_gpio_set_imask()
113 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); in brcmstb_gpio_set_imask()
114 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); in brcmstb_gpio_set_imask()
117 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) in brcmstb_gpio_to_irq() argument
119 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); in brcmstb_gpio_to_irq()
121 int hwirq = offset + (gc->base - priv->gpio_base); in brcmstb_gpio_to_irq()
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); in brcmstb_gpio_irq_mask() local
133 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_mask()
140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); in brcmstb_gpio_irq_unmask() local
141 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_unmask()
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); in brcmstb_gpio_irq_ack() local
149 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_ack()
153 gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask); in brcmstb_gpio_irq_ack()
158 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); in brcmstb_gpio_irq_set_type() local
159 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_set_type()
197 raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
199 iedge_config = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
201 iedge_insensitive = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
203 ilevel = bank->gc.read_reg(priv->reg_base + in brcmstb_gpio_irq_set_type()
206 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), in brcmstb_gpio_irq_set_type()
208 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), in brcmstb_gpio_irq_set_type()
210 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), in brcmstb_gpio_irq_set_type()
213 raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); in brcmstb_gpio_irq_set_type()
234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); in brcmstb_gpio_irq_set_wake() local
235 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_irq_set_wake()
266 int hwbase = bank->gc.base - priv->gpio_base; in brcmstb_gpio_irq_bank_handler()
306 i += bank->gc.ngpio; in brcmstb_gpio_hwirq_to_bank()
335 ret = irq_set_chip_data(irq, &bank->gc); in brcmstb_gpio_irq_map()
397 gpiochip_remove(&bank->gc); in brcmstb_gpio_remove()
402 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, in brcmstb_gpio_of_xlate() argument
405 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); in brcmstb_gpio_of_xlate()
406 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_of_xlate()
409 if (gc->of_gpio_n_cells != 2) { in brcmstb_gpio_of_xlate()
414 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) in brcmstb_gpio_of_xlate()
417 offset = gpiospec->args[0] - (gc->base - priv->gpio_base); in brcmstb_gpio_of_xlate()
418 if (offset >= gc->ngpio || offset < 0) in brcmstb_gpio_of_xlate()
500 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_save() local
504 bank->saved_regs[i] = gc->read_reg(priv->reg_base + in brcmstb_gpio_bank_save()
512 struct gpio_chip *gc; in brcmstb_gpio_quiesce() local
520 gc = &bank->gc; in brcmstb_gpio_quiesce()
530 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), in brcmstb_gpio_quiesce()
545 struct gpio_chip *gc = &bank->gc; in brcmstb_gpio_bank_restore() local
549 gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i), in brcmstb_gpio_bank_restore()
647 struct gpio_chip *gc; in brcmstb_gpio_probe() local
681 gc = &bank->gc; in brcmstb_gpio_probe()
682 err = bgpio_init(gc, dev, 4, in brcmstb_gpio_probe()
691 gc->owner = THIS_MODULE; in brcmstb_gpio_probe()
692 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); in brcmstb_gpio_probe()
693 if (!gc->label) { in brcmstb_gpio_probe()
697 gc->base = gpio_base; in brcmstb_gpio_probe()
698 gc->of_gpio_n_cells = 2; in brcmstb_gpio_probe()
699 gc->of_xlate = brcmstb_gpio_of_xlate; in brcmstb_gpio_probe()
701 gc->ngpio = MAX_GPIO_PER_BANK; in brcmstb_gpio_probe()
702 gc->offset = bank->id * MAX_GPIO_PER_BANK; in brcmstb_gpio_probe()
704 gc->to_irq = brcmstb_gpio_to_irq; in brcmstb_gpio_probe()
711 gc->write_reg(reg_base + GIO_MASK(bank->id), 0); in brcmstb_gpio_probe()
713 err = gpiochip_add_data(gc, bank); in brcmstb_gpio_probe()
719 gpio_base += gc->ngpio; in brcmstb_gpio_probe()
722 gc->base, gc->ngpio, bank->width); in brcmstb_gpio_probe()