Lines Matching refs:modifier
632 amdgpu_lookup_format_info(u32 format, uint64_t modifier) in amdgpu_lookup_format_info() argument
634 if (!IS_AMD_FMT_MOD(modifier)) in amdgpu_lookup_format_info()
637 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) in amdgpu_lookup_format_info()
642 if (AMD_FMT_MOD_GET(DCC, modifier)) in amdgpu_lookup_format_info()
704 uint64_t modifier = 0; in convert_tiling_flags_to_modifier() local
712 modifier = DRM_FORMAT_MOD_LINEAR; in convert_tiling_flags_to_modifier()
804 modifier = AMD_FMT_MOD | in convert_tiling_flags_to_modifier()
827 modifier |= AMD_FMT_MOD_SET(DCC, 1) | in convert_tiling_flags_to_modifier()
852 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1); in convert_tiling_flags_to_modifier()
864 modifier |= AMD_FMT_MOD_SET(RB, rb) | in convert_tiling_flags_to_modifier()
874 modifier); in convert_tiling_flags_to_modifier()
882 afb->base.modifier = modifier; in convert_tiling_flags_to_modifier()
921 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, in get_dcc_block_size() argument
924 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier); in get_dcc_block_size()
933 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); in get_dcc_block_size()
938 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); in get_dcc_block_size()
941 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) in get_dcc_block_size()
1005 uint64_t modifier = rfb->base.modifier; in amdgpu_display_verify_sizes() local
1013 if (modifier == DRM_FORMAT_MOD_LINEAR) { in amdgpu_display_verify_sizes()
1018 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); in amdgpu_display_verify_sizes()
1052 if (AMD_FMT_MOD_GET(DCC, modifier)) { in amdgpu_display_verify_sizes()
1053 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { in amdgpu_display_verify_sizes()
1054 block_size_log2 = get_dcc_block_size(modifier, false, false); in amdgpu_display_verify_sizes()
1064 block_size_log2 = get_dcc_block_size(modifier, true, true); in amdgpu_display_verify_sizes()
1066 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); in amdgpu_display_verify_sizes()
1068 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned); in amdgpu_display_verify_sizes()
1126 mode_cmd->modifier[0])) { in amdgpu_display_gem_fb_verify_and_init()
1129 &mode_cmd->pixel_format, mode_cmd->modifier[0]); in amdgpu_display_gem_fb_verify_and_init()