Lines Matching refs:rlc
39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
98 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
99 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
100 (void **)&adev->gfx.rlc.sr_ptr); in amdgpu_gfx_rlc_init_sr()
108 src_ptr = adev->gfx.rlc.reg_list; in amdgpu_gfx_rlc_init_sr()
109 dst_ptr = adev->gfx.rlc.sr_ptr; in amdgpu_gfx_rlc_init_sr()
110 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in amdgpu_gfx_rlc_init_sr()
112 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); in amdgpu_gfx_rlc_init_sr()
113 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); in amdgpu_gfx_rlc_init_sr()
132 adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev); in amdgpu_gfx_rlc_init_csb()
136 &adev->gfx.rlc.clear_state_obj, in amdgpu_gfx_rlc_init_csb()
137 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_init_csb()
138 (void **)&adev->gfx.rlc.cs_ptr); in amdgpu_gfx_rlc_init_csb()
160 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in amdgpu_gfx_rlc_init_cpt()
163 &adev->gfx.rlc.cp_table_obj, in amdgpu_gfx_rlc_init_cpt()
164 &adev->gfx.rlc.cp_table_gpu_addr, in amdgpu_gfx_rlc_init_cpt()
165 (void **)&adev->gfx.rlc.cp_table_ptr); in amdgpu_gfx_rlc_init_cpt()
174 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); in amdgpu_gfx_rlc_init_cpt()
175 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); in amdgpu_gfx_rlc_init_cpt()
195 max_me = adev->gfx.rlc.funcs->get_cp_table_num(adev); in amdgpu_gfx_rlc_setup_cp_table()
198 dst_ptr = adev->gfx.rlc.cp_table_ptr; in amdgpu_gfx_rlc_setup_cp_table()
262 if (adev->gfx.rlc.save_restore_obj) { in amdgpu_gfx_rlc_fini()
263 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_fini()
264 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_fini()
265 (void **)&adev->gfx.rlc.sr_ptr); in amdgpu_gfx_rlc_fini()
269 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in amdgpu_gfx_rlc_fini()
270 &adev->gfx.rlc.clear_state_gpu_addr, in amdgpu_gfx_rlc_fini()
271 (void **)&adev->gfx.rlc.cs_ptr); in amdgpu_gfx_rlc_fini()
274 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in amdgpu_gfx_rlc_fini()
275 &adev->gfx.rlc.cp_table_gpu_addr, in amdgpu_gfx_rlc_fini()
276 (void **)&adev->gfx.rlc.cp_table_ptr); in amdgpu_gfx_rlc_fini()
291 adev->gfx.rlc.save_and_restore_offset = in amdgpu_gfx_rlc_init_microcode_v2_0()
293 adev->gfx.rlc.clear_state_descriptor_offset = in amdgpu_gfx_rlc_init_microcode_v2_0()
295 adev->gfx.rlc.avail_scratch_ram_locations = in amdgpu_gfx_rlc_init_microcode_v2_0()
297 adev->gfx.rlc.reg_restore_list_size = in amdgpu_gfx_rlc_init_microcode_v2_0()
299 adev->gfx.rlc.reg_list_format_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
301 adev->gfx.rlc.reg_list_format_separate_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
303 adev->gfx.rlc.starting_offsets_start = in amdgpu_gfx_rlc_init_microcode_v2_0()
305 adev->gfx.rlc.reg_list_format_size_bytes = in amdgpu_gfx_rlc_init_microcode_v2_0()
307 adev->gfx.rlc.reg_list_size_bytes = in amdgpu_gfx_rlc_init_microcode_v2_0()
309 adev->gfx.rlc.register_list_format = in amdgpu_gfx_rlc_init_microcode_v2_0()
310 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + in amdgpu_gfx_rlc_init_microcode_v2_0()
311 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); in amdgpu_gfx_rlc_init_microcode_v2_0()
312 if (!adev->gfx.rlc.register_list_format) { in amdgpu_gfx_rlc_init_microcode_v2_0()
320 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); in amdgpu_gfx_rlc_init_microcode_v2_0()
322 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; in amdgpu_gfx_rlc_init_microcode_v2_0()
327 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); in amdgpu_gfx_rlc_init_microcode_v2_0()
351 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in amdgpu_gfx_rlc_init_microcode_v2_1()
352 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in amdgpu_gfx_rlc_init_microcode_v2_1()
355 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in amdgpu_gfx_rlc_init_microcode_v2_1()
356 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()
359 …adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_b… in amdgpu_gfx_rlc_init_microcode_v2_1()
360 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()
361 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in amdgpu_gfx_rlc_init_microcode_v2_1()
365 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
370 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
373 if (adev->gfx.rlc.save_restore_list_gpm_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
378 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
381 if (adev->gfx.rlc.save_restore_list_srm_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_1()
386 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_1()
397 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
398 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
399 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
400 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()
403 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_2()
408 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_2()
411 if (adev->gfx.rlc.rlc_dram_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_2()
416 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_2()
429 adev->gfx.rlc.rlcp_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcp_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
430 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
434 adev->gfx.rlc.rlcv_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlcv_ucode_size_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
435 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()
438 if (adev->gfx.rlc.rlcp_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_3()
443 ALIGN(adev->gfx.rlc.rlcp_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_3()
446 if (adev->gfx.rlc.rlcv_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_3()
451 ALIGN(adev->gfx.rlc.rlcv_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_3()
462 …adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_si… in amdgpu_gfx_rlc_init_microcode_v2_4()
463 …adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_uco… in amdgpu_gfx_rlc_init_microcode_v2_4()
464 …adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
465 …adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
466 …adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
467 …adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
468 …adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
469 …adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
470 …adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_byt… in amdgpu_gfx_rlc_init_microcode_v2_4()
471 …adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()
474 if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
479 ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
482 if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
487 ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
490 if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
495 ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
498 if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
503 ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
506 if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) { in amdgpu_gfx_rlc_init_microcode_v2_4()
511 ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE); in amdgpu_gfx_rlc_init_microcode_v2_4()
530 adev->gfx.rlc.is_rlc_v2_1 = true; in amdgpu_gfx_rlc_init_microcode()