Lines Matching refs:vcn
91 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name); in amdgpu_vcn_early_init()
93 amdgpu_ucode_release(&adev->vcn.fw); in amdgpu_vcn_early_init()
106 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler); in amdgpu_vcn_sw_init()
107 mutex_init(&adev->vcn.vcn_pg_lock); in amdgpu_vcn_sw_init()
108 mutex_init(&adev->vcn.vcn1_jpeg1_workaround); in amdgpu_vcn_sw_init()
109 atomic_set(&adev->vcn.total_submission_cnt, 0); in amdgpu_vcn_sw_init()
110 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in amdgpu_vcn_sw_init()
111 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0); in amdgpu_vcn_sw_init()
115 adev->vcn.indirect_sram = true; in amdgpu_vcn_sw_init()
117 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in amdgpu_vcn_sw_init()
118 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version); in amdgpu_vcn_sw_init()
164 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_sw_init()
165 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_vcn_sw_init()
171 &adev->vcn.inst[i].vcpu_bo, in amdgpu_vcn_sw_init()
172 &adev->vcn.inst[i].gpu_addr, in amdgpu_vcn_sw_init()
173 &adev->vcn.inst[i].cpu_addr); in amdgpu_vcn_sw_init()
179 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr + in amdgpu_vcn_sw_init()
181 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr + in amdgpu_vcn_sw_init()
184 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size; in amdgpu_vcn_sw_init()
187 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE; in amdgpu_vcn_sw_init()
188 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE; in amdgpu_vcn_sw_init()
189 adev->vcn.inst[i].fw_shared.log_offset = log_offset; in amdgpu_vcn_sw_init()
192 if (adev->vcn.indirect_sram) { in amdgpu_vcn_sw_init()
196 &adev->vcn.inst[i].dpg_sram_bo, in amdgpu_vcn_sw_init()
197 &adev->vcn.inst[i].dpg_sram_gpu_addr, in amdgpu_vcn_sw_init()
198 &adev->vcn.inst[i].dpg_sram_cpu_addr); in amdgpu_vcn_sw_init()
213 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_sw_fini()
214 if (adev->vcn.harvest_config & (1 << j)) in amdgpu_vcn_sw_fini()
217 if (adev->vcn.indirect_sram) { in amdgpu_vcn_sw_fini()
218 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, in amdgpu_vcn_sw_fini()
219 &adev->vcn.inst[j].dpg_sram_gpu_addr, in amdgpu_vcn_sw_fini()
220 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr); in amdgpu_vcn_sw_fini()
222 kvfree(adev->vcn.inst[j].saved_bo); in amdgpu_vcn_sw_fini()
224 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo, in amdgpu_vcn_sw_fini()
225 &adev->vcn.inst[j].gpu_addr, in amdgpu_vcn_sw_fini()
226 (void **)&adev->vcn.inst[j].cpu_addr); in amdgpu_vcn_sw_fini()
228 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec); in amdgpu_vcn_sw_fini()
230 for (i = 0; i < adev->vcn.num_enc_rings; ++i) in amdgpu_vcn_sw_fini()
231 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]); in amdgpu_vcn_sw_fini()
234 amdgpu_ucode_release(&adev->vcn.fw); in amdgpu_vcn_sw_fini()
235 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround); in amdgpu_vcn_sw_fini()
236 mutex_destroy(&adev->vcn.vcn_pg_lock); in amdgpu_vcn_sw_fini()
256 int vcn_config = adev->vcn.vcn_config[vcn_instance]; in amdgpu_vcn_is_disabled_vcn()
275 cancel_delayed_work_sync(&adev->vcn.idle_work); in amdgpu_vcn_suspend()
277 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_suspend()
278 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_vcn_suspend()
280 if (adev->vcn.inst[i].vcpu_bo == NULL) in amdgpu_vcn_suspend()
283 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); in amdgpu_vcn_suspend()
284 ptr = adev->vcn.inst[i].cpu_addr; in amdgpu_vcn_suspend()
286 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL); in amdgpu_vcn_suspend()
287 if (!adev->vcn.inst[i].saved_bo) in amdgpu_vcn_suspend()
291 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size); in amdgpu_vcn_suspend()
304 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_resume()
305 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_vcn_resume()
307 if (adev->vcn.inst[i].vcpu_bo == NULL) in amdgpu_vcn_resume()
310 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo); in amdgpu_vcn_resume()
311 ptr = adev->vcn.inst[i].cpu_addr; in amdgpu_vcn_resume()
313 if (adev->vcn.inst[i].saved_bo != NULL) { in amdgpu_vcn_resume()
315 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size); in amdgpu_vcn_resume()
318 kvfree(adev->vcn.inst[i].saved_bo); in amdgpu_vcn_resume()
319 adev->vcn.inst[i].saved_bo = NULL; in amdgpu_vcn_resume()
324 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in amdgpu_vcn_resume()
328 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset, in amdgpu_vcn_resume()
344 container_of(work, struct amdgpu_device, vcn.idle_work.work); in amdgpu_vcn_idle_work_handler()
349 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_idle_work_handler()
350 if (adev->vcn.harvest_config & (1 << j)) in amdgpu_vcn_idle_work_handler()
353 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { in amdgpu_vcn_idle_work_handler()
354 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]); in amdgpu_vcn_idle_work_handler()
361 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt))) in amdgpu_vcn_idle_work_handler()
366 adev->vcn.pause_dpg_mode(adev, j, &new_state); in amdgpu_vcn_idle_work_handler()
369 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec); in amdgpu_vcn_idle_work_handler()
373 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) { in amdgpu_vcn_idle_work_handler()
381 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); in amdgpu_vcn_idle_work_handler()
390 atomic_inc(&adev->vcn.total_submission_cnt); in amdgpu_vcn_ring_begin_use()
392 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) { in amdgpu_vcn_ring_begin_use()
399 mutex_lock(&adev->vcn.vcn_pg_lock); in amdgpu_vcn_ring_begin_use()
407 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); in amdgpu_vcn_ring_begin_use()
413 for (i = 0; i < adev->vcn.num_enc_rings; ++i) in amdgpu_vcn_ring_begin_use()
414 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]); in amdgpu_vcn_ring_begin_use()
416 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt)) in amdgpu_vcn_ring_begin_use()
422 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state); in amdgpu_vcn_ring_begin_use()
424 mutex_unlock(&adev->vcn.vcn_pg_lock); in amdgpu_vcn_ring_begin_use()
431 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt); in amdgpu_vcn_ring_end_use()
433 atomic_dec(&ring->adev->vcn.total_submission_cnt); in amdgpu_vcn_ring_end_use()
435 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); in amdgpu_vcn_ring_end_use()
449 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); in amdgpu_vcn_dec_ring_test_ring()
453 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); in amdgpu_vcn_dec_ring_test_ring()
457 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); in amdgpu_vcn_dec_ring_test_ring()
518 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); in amdgpu_vcn_dec_send_msg()
520 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); in amdgpu_vcn_dec_send_msg()
522 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0); in amdgpu_vcn_dec_send_msg()
525 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0); in amdgpu_vcn_dec_send_msg()
1010 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; in amdgpu_vcn_setup_ucode()
1012 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_setup_ucode()
1013 if (adev->vcn.harvest_config & (1 << i)) in amdgpu_vcn_setup_ucode()
1022 adev->firmware.ucode[idx].fw = adev->vcn.fw; in amdgpu_vcn_setup_ucode()
1037 struct amdgpu_vcn_inst *vcn; in amdgpu_debugfs_vcn_fwlog_read() local
1043 vcn = file_inode(f)->i_private; in amdgpu_debugfs_vcn_fwlog_read()
1044 if (!vcn) in amdgpu_debugfs_vcn_fwlog_read()
1047 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log) in amdgpu_debugfs_vcn_fwlog_read()
1050 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; in amdgpu_debugfs_vcn_fwlog_read()
1102 struct amdgpu_vcn_inst *vcn) in amdgpu_debugfs_vcn_fwlog_init() argument
1110 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn, in amdgpu_debugfs_vcn_fwlog_init()
1116 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn) in amdgpu_vcn_fwlog_init() argument
1119 volatile uint32_t *flag = vcn->fw_shared.cpu_addr; in amdgpu_vcn_fwlog_init()
1120 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size; in amdgpu_vcn_fwlog_init()
1121 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size; in amdgpu_vcn_fwlog_init()
1123 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr in amdgpu_vcn_fwlog_init()
1124 + vcn->fw_shared.log_offset; in amdgpu_vcn_fwlog_init()
1143 struct ras_common_if *ras_if = adev->vcn.ras_if; in amdgpu_vcn_process_poison_irq()
1167 if (!adev->vcn.ras) in amdgpu_vcn_set_ras_funcs()
1170 amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block); in amdgpu_vcn_set_ras_funcs()
1172 strcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn"); in amdgpu_vcn_set_ras_funcs()
1173 adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in amdgpu_vcn_set_ras_funcs()
1174 adev->vcn.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_vcn_set_ras_funcs()
1175 adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm; in amdgpu_vcn_set_ras_funcs()
1178 if (!adev->vcn.ras->ras_block.ras_late_init) in amdgpu_vcn_set_ras_funcs()
1179 adev->vcn.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; in amdgpu_vcn_set_ras_funcs()