Lines Matching refs:sdma
77 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_free_microcode()
78 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in cik_sdma_free_microcode()
134 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_init_microcode()
139 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); in cik_sdma_init_microcode()
146 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_init_microcode()
147 amdgpu_ucode_release(&adev->sdma.instance[i].fw); in cik_sdma_init_microcode()
199 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in cik_sdma_ring_insert_nop() local
203 if (sdma && sdma->burst_nop && (i == 0)) in cik_sdma_ring_insert_nop()
313 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_stop()
370 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_ctx_switch_enable()
408 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_enable()
433 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_resume()
434 ring = &adev->sdma.instance[i].ring; in cik_sdma_gfx_resume()
498 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_resume()
499 ring = &adev->sdma.instance[i].ring; in cik_sdma_gfx_resume()
543 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_load_microcode()
544 if (!adev->sdma.instance[i].fw) in cik_sdma_load_microcode()
546 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; in cik_sdma_load_microcode()
549 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); in cik_sdma_load_microcode()
550 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); in cik_sdma_load_microcode()
551 if (adev->sdma.instance[i].feature_version >= 20) in cik_sdma_load_microcode()
552 adev->sdma.instance[i].burst_nop = true; in cik_sdma_load_microcode()
554 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in cik_sdma_load_microcode()
558 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); in cik_sdma_load_microcode()
805 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); in cik_sdma_ring_pad_ib() local
811 if (sdma && sdma->burst_nop && (i == 0)) in cik_sdma_ring_pad_ib()
931 adev->sdma.num_instances = SDMA_MAX_INSTANCE; in cik_sdma_early_init()
955 &adev->sdma.trap_irq); in cik_sdma_sw_init()
961 &adev->sdma.illegal_inst_irq); in cik_sdma_sw_init()
967 &adev->sdma.illegal_inst_irq); in cik_sdma_sw_init()
971 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_sw_init()
972 ring = &adev->sdma.instance[i].ring; in cik_sdma_sw_init()
976 &adev->sdma.trap_irq, in cik_sdma_sw_init()
992 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_sw_fini()
993 amdgpu_ring_fini(&adev->sdma.instance[i].ring); in cik_sdma_sw_fini()
1163 amdgpu_fence_process(&adev->sdma.instance[0].ring); in cik_sdma_process_trap_irq()
1176 amdgpu_fence_process(&adev->sdma.instance[1].ring); in cik_sdma_process_trap_irq()
1199 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); in cik_sdma_process_illegal_inst_irq()
1272 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_set_ring_funcs()
1273 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; in cik_sdma_set_ring_funcs()
1274 adev->sdma.instance[i].ring.me = i; in cik_sdma_set_ring_funcs()
1289 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; in cik_sdma_set_irq_funcs()
1290 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; in cik_sdma_set_irq_funcs()
1291 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; in cik_sdma_set_irq_funcs()
1357 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in cik_sdma_set_buffer_funcs()
1373 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_set_vm_pte_funcs()
1375 &adev->sdma.instance[i].ring.sched; in cik_sdma_set_vm_pte_funcs()
1377 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in cik_sdma_set_vm_pte_funcs()