Lines Matching refs:hpd
90 uint32_t hpd; member
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
285 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_sense() argument
289 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_sense()
292 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v10_0_hpd_sense()
308 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_set_polarity() argument
311 bool connected = dce_v10_0_hpd_sense(adev, hpd); in dce_v10_0_hpd_set_polarity()
313 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_set_polarity()
316 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
321 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
343 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_init()
353 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
355 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
359 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
361 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
363 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
370 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
372 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
374 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
398 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_fini()
401 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_fini()
403 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_fini()
406 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_fini()
3053 unsigned hpd, in dce_v10_0_set_hpd_irq_state() argument
3058 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_set_hpd_irq_state()
3059 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_set_hpd_irq_state()
3065 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3067 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3070 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3072 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3206 int hpd) in dce_v10_0_hpd_int_ack() argument
3210 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_int_ack()
3211 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_hpd_int_ack()
3215 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3217 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
3293 unsigned hpd; in dce_v10_0_hpd_irq() local
3300 hpd = entry->src_data[0]; in dce_v10_0_hpd_irq()
3301 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3302 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
3305 dce_v10_0_hpd_int_ack(adev, hpd); in dce_v10_0_hpd_irq()
3307 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v10_0_hpd_irq()