Lines Matching refs:gfx
3571 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { in gfx10_kiq_unmap_queues()
3639 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3894 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3895 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3896 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
3897 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
3898 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_free_microcode()
3899 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_free_microcode()
3901 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
3906 adev->gfx.cp_fw_write_wait = false; in gfx_v10_0_check_fw_write_wait()
3914 if ((adev->gfx.me_fw_version >= 0x00000046) && in gfx_v10_0_check_fw_write_wait()
3915 (adev->gfx.me_feature_version >= 27) && in gfx_v10_0_check_fw_write_wait()
3916 (adev->gfx.pfp_fw_version >= 0x00000068) && in gfx_v10_0_check_fw_write_wait()
3917 (adev->gfx.pfp_feature_version >= 27) && in gfx_v10_0_check_fw_write_wait()
3918 (adev->gfx.mec_fw_version >= 0x0000005b) && in gfx_v10_0_check_fw_write_wait()
3919 (adev->gfx.mec_feature_version >= 27)) in gfx_v10_0_check_fw_write_wait()
3920 adev->gfx.cp_fw_write_wait = true; in gfx_v10_0_check_fw_write_wait()
3930 adev->gfx.cp_fw_write_wait = true; in gfx_v10_0_check_fw_write_wait()
3936 if (!adev->gfx.cp_fw_write_wait) in gfx_v10_0_check_fw_write_wait()
3987 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name); in gfx_v10_0_init_microcode()
3993 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name); in gfx_v10_0_init_microcode()
3999 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name); in gfx_v10_0_init_microcode()
4006 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); in gfx_v10_0_init_microcode()
4016 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_init_microcode()
4025 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); in gfx_v10_0_init_microcode()
4032 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name); in gfx_v10_0_init_microcode()
4038 adev->gfx.mec2_fw = NULL; in gfx_v10_0_init_microcode()
4046 amdgpu_ucode_release(&adev->gfx.pfp_fw); in gfx_v10_0_init_microcode()
4047 amdgpu_ucode_release(&adev->gfx.me_fw); in gfx_v10_0_init_microcode()
4048 amdgpu_ucode_release(&adev->gfx.ce_fw); in gfx_v10_0_init_microcode()
4049 amdgpu_ucode_release(&adev->gfx.rlc_fw); in gfx_v10_0_init_microcode()
4050 amdgpu_ucode_release(&adev->gfx.mec_fw); in gfx_v10_0_init_microcode()
4051 amdgpu_ucode_release(&adev->gfx.mec2_fw); in gfx_v10_0_init_microcode()
4097 if (adev->gfx.rlc.cs_data == NULL) in gfx_v10_0_get_csb_buffer()
4109 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v10_0_get_csb_buffer()
4128 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); in gfx_v10_0_get_csb_buffer()
4140 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v10_0_rlc_fini()
4141 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
4142 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v10_0_rlc_fini()
4145 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v10_0_rlc_fini()
4146 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v10_0_rlc_fini()
4147 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v10_0_rlc_fini()
4154 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4171 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4179 adev->gfx.rlc.cs_data = gfx10_cs_data; in gfx_v10_0_rlc_init()
4181 cs_data = adev->gfx.rlc.cs_data; in gfx_v10_0_rlc_init()
4191 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v10_0_rlc_init()
4192 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); in gfx_v10_0_rlc_init()
4200 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); in gfx_v10_0_mec_fini()
4201 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); in gfx_v10_0_mec_fini()
4206 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); in gfx_v10_0_me_init()
4222 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v10_0_mec_init()
4226 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; in gfx_v10_0_mec_init()
4231 &adev->gfx.mec.hpd_eop_obj, in gfx_v10_0_mec_init()
4232 &adev->gfx.mec.hpd_eop_gpu_addr, in gfx_v10_0_mec_init()
4242 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
4243 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); in gfx_v10_0_mec_init()
4247 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_mec_init()
4249 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v10_0_mec_init()
4255 &adev->gfx.mec.mec_fw_obj, in gfx_v10_0_mec_init()
4256 &adev->gfx.mec.mec_fw_gpu_addr, in gfx_v10_0_mec_init()
4266 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
4267 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); in gfx_v10_0_mec_init()
4383 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4384 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4385 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4386 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v10_0_gpu_early_init()
4387 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4398 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4399 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4400 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4401 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v10_0_gpu_early_init()
4402 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4404 adev->gfx.config.gb_addr_config_fields.num_pkrs = in gfx_v10_0_gpu_early_init()
4409 adev->gfx.config.max_hw_contexts = 8; in gfx_v10_0_gpu_early_init()
4410 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v10_0_gpu_early_init()
4411 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v10_0_gpu_early_init()
4412 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; in gfx_v10_0_gpu_early_init()
4413 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v10_0_gpu_early_init()
4421 adev->gfx.config.gb_addr_config = gb_addr_config; in gfx_v10_0_gpu_early_init()
4423 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v10_0_gpu_early_init()
4424 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4427 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
4428 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v10_0_gpu_early_init()
4430 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v10_0_gpu_early_init()
4431 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4433 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v10_0_gpu_early_init()
4434 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4436 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()
4437 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4439 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v10_0_gpu_early_init()
4440 REG_GET_FIELD(adev->gfx.config.gb_addr_config, in gfx_v10_0_gpu_early_init()
4451 ring = &adev->gfx.gfx_ring[ring_id]; in gfx_v10_0_gfx_ring_init()
4469 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v10_0_gfx_ring_init()
4480 ring = &adev->gfx.compute_ring[ring_id]; in gfx_v10_0_compute_ring_init()
4490 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr in gfx_v10_0_compute_ring_init()
4495 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) in gfx_v10_0_compute_ring_init()
4500 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, in gfx_v10_0_compute_ring_init()
4516 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4517 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4518 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4519 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4520 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4521 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4531 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4532 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4533 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4534 adev->gfx.mec.num_mec = 2; in gfx_v10_0_sw_init()
4535 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4536 adev->gfx.mec.num_queue_per_pipe = 4; in gfx_v10_0_sw_init()
4539 adev->gfx.me.num_me = 1; in gfx_v10_0_sw_init()
4540 adev->gfx.me.num_pipe_per_me = 1; in gfx_v10_0_sw_init()
4541 adev->gfx.me.num_queue_per_pipe = 1; in gfx_v10_0_sw_init()
4542 adev->gfx.mec.num_mec = 1; in gfx_v10_0_sw_init()
4543 adev->gfx.mec.num_pipe_per_mec = 4; in gfx_v10_0_sw_init()
4544 adev->gfx.mec.num_queue_per_pipe = 8; in gfx_v10_0_sw_init()
4551 &adev->gfx.kiq.irq); in gfx_v10_0_sw_init()
4558 &adev->gfx.eop_irq); in gfx_v10_0_sw_init()
4564 &adev->gfx.priv_reg_irq); in gfx_v10_0_sw_init()
4570 &adev->gfx.priv_inst_irq); in gfx_v10_0_sw_init()
4574 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; in gfx_v10_0_sw_init()
4578 if (adev->gfx.rlc.funcs) { in gfx_v10_0_sw_init()
4579 if (adev->gfx.rlc.funcs->init) { in gfx_v10_0_sw_init()
4580 r = adev->gfx.rlc.funcs->init(adev); in gfx_v10_0_sw_init()
4595 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v10_0_sw_init()
4596 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
4597 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v10_0_sw_init()
4612 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v10_0_sw_init()
4613 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v10_0_sw_init()
4614 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v10_0_sw_init()
4636 kiq = &adev->gfx.kiq; in gfx_v10_0_sw_init()
4653 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; in gfx_v10_0_sw_init()
4662 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, in gfx_v10_0_pfp_fini()
4663 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v10_0_pfp_fini()
4664 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v10_0_pfp_fini()
4669 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, in gfx_v10_0_ce_fini()
4670 &adev->gfx.ce.ce_fw_gpu_addr, in gfx_v10_0_ce_fini()
4671 (void **)&adev->gfx.ce.ce_fw_ptr); in gfx_v10_0_ce_fini()
4676 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, in gfx_v10_0_me_fini()
4677 &adev->gfx.me.me_fw_gpu_addr, in gfx_v10_0_me_fini()
4678 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v10_0_me_fini()
4686 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_sw_fini()
4687 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); in gfx_v10_0_sw_fini()
4688 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_sw_fini()
4689 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); in gfx_v10_0_sw_fini()
4694 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); in gfx_v10_0_sw_fini()
4749 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / in gfx_v10_0_get_rb_active_bitmap()
4750 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
4761 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / in gfx_v10_0_setup_rb()
4762 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
4765 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_setup_rb()
4766 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
4767 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
4775 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
4782 adev->gfx.config.backend_enable_mask = active_rbs; in gfx_v10_0_setup_rb()
4783 adev->gfx.config.num_rbs = hweight32(active_rbs); in gfx_v10_0_setup_rb()
4801 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
4802 adev->gfx.config.num_sc_per_sh; in gfx_v10_0_init_pa_sc_tile_steering_override()
4806 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; in gfx_v10_0_init_pa_sc_tile_steering_override()
4808 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; in gfx_v10_0_init_pa_sc_tile_steering_override()
4881 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; in gfx_v10_0_tcp_harvest()
4906 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_tcp_harvest()
4907 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
4958 adev->gfx.config.tcc_disabled_mask = in gfx_v10_0_get_tcc_info()
4971 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); in gfx_v10_0_constants_init()
4973 adev->gfx.config.pa_sc_tile_steering_override = in gfx_v10_0_constants_init()
5024 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v10_0_init_csb()
5029 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5031 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
5032 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5035 adev->gfx.rlc.clear_state_gpu_addr >> 32); in gfx_v10_0_init_csb()
5037 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v10_0_init_csb()
5038 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5109 if (!adev->gfx.rlc_fw) in gfx_v10_0_rlc_load_microcode()
5112 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_rlc_load_microcode()
5115 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v10_0_rlc_load_microcode()
5126 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v10_0_rlc_load_microcode()
5152 adev->gfx.rlc.funcs->stop(adev); in gfx_v10_0_rlc_resume()
5174 adev->gfx.rlc.funcs->start(adev); in gfx_v10_0_rlc_resume()
5198 &adev->gfx.rlc.rlc_toc_bo, in gfx_v10_0_parse_rlc_toc()
5199 &adev->gfx.rlc.rlc_toc_gpu_addr, in gfx_v10_0_parse_rlc_toc()
5200 (void **)&adev->gfx.rlc.rlc_toc_buf); in gfx_v10_0_parse_rlc_toc()
5207 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); in gfx_v10_0_parse_rlc_toc()
5209 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; in gfx_v10_0_parse_rlc_toc()
5260 &adev->gfx.rlc.rlc_autoload_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5261 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5262 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v10_0_rlc_backdoor_autoload_buffer_init()
5273 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5274 &adev->gfx.rlc.rlc_toc_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5275 (void **)&adev->gfx.rlc.rlc_toc_buf); in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5276 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5277 &adev->gfx.rlc.rlc_autoload_gpu_addr, in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5278 (void **)&adev->gfx.rlc.rlc_autoload_ptr); in gfx_v10_0_rlc_backdoor_autoload_buffer_fini()
5288 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; in gfx_v10_0_rlc_backdoor_autoload_copy_ucode()
5313 data = adev->gfx.rlc.rlc_toc_buf; in gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode()
5330 adev->gfx.pfp_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5331 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5340 adev->gfx.ce_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5341 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5350 adev->gfx.me_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5351 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5360 adev->gfx.rlc_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5361 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5370 adev->gfx.mec_fw->data; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5371 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
5427 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; in gfx_v10_0_rlc_backdoor_autoload_enable()
5476 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_me_cache()
5513 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_ce_cache()
5550 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache()
5587 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + in gfx_v10_0_rlc_backdoor_autoload_config_mec_cache()
5680 adev->gfx.pfp_fw->data; in gfx_v10_0_cp_gfx_load_pfp_microcode()
5684 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + in gfx_v10_0_cp_gfx_load_pfp_microcode()
5690 &adev->gfx.pfp.pfp_fw_obj, in gfx_v10_0_cp_gfx_load_pfp_microcode()
5691 &adev->gfx.pfp.pfp_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_pfp_microcode()
5692 (void **)&adev->gfx.pfp.pfp_fw_ptr); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5699 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5701 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5702 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5733 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5735 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5743 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v10_0_cp_gfx_load_pfp_microcode()
5758 adev->gfx.ce_fw->data; in gfx_v10_0_cp_gfx_load_ce_microcode()
5762 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + in gfx_v10_0_cp_gfx_load_ce_microcode()
5768 &adev->gfx.ce.ce_fw_obj, in gfx_v10_0_cp_gfx_load_ce_microcode()
5769 &adev->gfx.ce.ce_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_ce_microcode()
5770 (void **)&adev->gfx.ce.ce_fw_ptr); in gfx_v10_0_cp_gfx_load_ce_microcode()
5777 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_ce_microcode()
5779 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); in gfx_v10_0_cp_gfx_load_ce_microcode()
5780 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); in gfx_v10_0_cp_gfx_load_ce_microcode()
5810 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_ce_microcode()
5812 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_ce_microcode()
5820 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); in gfx_v10_0_cp_gfx_load_ce_microcode()
5835 adev->gfx.me_fw->data; in gfx_v10_0_cp_gfx_load_me_microcode()
5839 fw_data = (const __le32 *)(adev->gfx.me_fw->data + in gfx_v10_0_cp_gfx_load_me_microcode()
5845 &adev->gfx.me.me_fw_obj, in gfx_v10_0_cp_gfx_load_me_microcode()
5846 &adev->gfx.me.me_fw_gpu_addr, in gfx_v10_0_cp_gfx_load_me_microcode()
5847 (void **)&adev->gfx.me.me_fw_ptr); in gfx_v10_0_cp_gfx_load_me_microcode()
5854 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); in gfx_v10_0_cp_gfx_load_me_microcode()
5856 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); in gfx_v10_0_cp_gfx_load_me_microcode()
5857 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); in gfx_v10_0_cp_gfx_load_me_microcode()
5887 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); in gfx_v10_0_cp_gfx_load_me_microcode()
5889 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); in gfx_v10_0_cp_gfx_load_me_microcode()
5897 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v10_0_cp_gfx_load_me_microcode()
5906 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v10_0_cp_gfx_load_microcode()
5942 adev->gfx.config.max_hw_contexts - 1); in gfx_v10_0_cp_gfx_start()
5947 ring = &adev->gfx.gfx_ring[0]; in gfx_v10_0_cp_gfx_start()
5979 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); in gfx_v10_0_cp_gfx_start()
5995 if (adev->gfx.num_gfx_rings > 1) { in gfx_v10_0_cp_gfx_start()
5997 ring = &adev->gfx.gfx_ring[1]; in gfx_v10_0_cp_gfx_start()
6087 ring = &adev->gfx.gfx_ring[0]; in gfx_v10_0_cp_gfx_resume()
6126 if (adev->gfx.num_gfx_rings > 1) { in gfx_v10_0_cp_gfx_resume()
6130 ring = &adev->gfx.gfx_ring[1]; in gfx_v10_0_cp_gfx_resume()
6169 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_gfx_resume()
6170 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_gfx_resume()
6215 adev->gfx.kiq.ring.sched.ready = false; in gfx_v10_0_cp_compute_enable()
6228 if (!adev->gfx.mec_fw) in gfx_v10_0_cp_compute_load_microcode()
6233 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; in gfx_v10_0_cp_compute_load_microcode()
6237 (adev->gfx.mec_fw->data + in gfx_v10_0_cp_compute_load_microcode()
6268 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & in gfx_v10_0_cp_compute_load_microcode()
6271 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); in gfx_v10_0_cp_compute_load_microcode()
6280 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v10_0_cp_compute_load_microcode()
6477 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v10_0_gfx_init_queue()
6498 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v10_0_gfx_init_queue()
6499 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
6502 if (adev->gfx.me.mqd_backup[mqd_idx]) in gfx_v10_0_gfx_init_queue()
6503 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_gfx_init_queue()
6525 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v10_0_kiq_enable_kgq()
6526 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v10_0_kiq_enable_kgq()
6533 adev->gfx.num_gfx_rings); in gfx_v10_0_kiq_enable_kgq()
6539 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_kiq_enable_kgq()
6540 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); in gfx_v10_0_kiq_enable_kgq()
6551 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_async_gfx_ring_resume()
6552 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_async_gfx_ring_resume()
6577 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_async_gfx_ring_resume()
6578 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_async_gfx_ring_resume()
6819 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kiq_init_queue()
6820 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
6842 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kiq_init_queue()
6843 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kiq_init_queue()
6853 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v10_0_kcq_init_queue()
6863 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
6864 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
6867 if (adev->gfx.mec.mqd_backup[mqd_idx]) in gfx_v10_0_kcq_init_queue()
6868 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v10_0_kcq_init_queue()
6886 ring = &adev->gfx.kiq.ring; in gfx_v10_0_kiq_resume()
6911 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_kcq_resume()
6912 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_kcq_resume()
6973 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_cp_resume()
6974 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_cp_resume()
6980 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_cp_resume()
6981 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_cp_resume()
7244 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v10_0_kiq_disable_kgq()
7252 adev->gfx.num_gfx_rings)) in gfx_v10_0_kiq_disable_kgq()
7255 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_kiq_disable_kgq()
7256 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], in gfx_v10_0_kiq_disable_kgq()
7271 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v10_0_hw_fini()
7272 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v10_0_hw_fini()
7517 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; in gfx_v10_0_early_init()
7525 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; in gfx_v10_0_early_init()
7535 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; in gfx_v10_0_early_init()
7541 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v10_0_early_init()
7562 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v10_0_late_init()
7566 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v10_0_late_init()
8650 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in gfx_v10_0_ring_preempt_ib()
8705 gfx[0].gfx_meta_data) + in gfx_v10_0_ring_emit_ce_meta()
8743 gfx[0].gfx_meta_data) + in gfx_v10_0_ring_emit_de_meta()
8751 gfx[0].gds_backup) + in gfx_v10_0_ring_emit_de_meta()
8847 fw_version_ok = adev->gfx.cp_fw_write_wait; in gfx_v10_0_ring_emit_reg_write_reg_wait()
9038 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v10_0_eop_irq()
9040 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); in gfx_v10_0_eop_irq()
9044 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_eop_irq()
9045 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_eop_irq()
9113 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v10_0_handle_priv_fault()
9114 ring = &adev->gfx.gfx_ring[i]; in gfx_v10_0_handle_priv_fault()
9122 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_handle_priv_fault()
9123 ring = &adev->gfx.compute_ring[i]; in gfx_v10_0_handle_priv_fault()
9158 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); in gfx_v10_0_kiq_set_interrupt_state()
9202 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); in gfx_v10_0_kiq_irq()
9382 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; in gfx_v10_0_set_ring_funcs()
9384 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v10_0_set_ring_funcs()
9385 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; in gfx_v10_0_set_ring_funcs()
9387 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_set_ring_funcs()
9388 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; in gfx_v10_0_set_ring_funcs()
9413 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; in gfx_v10_0_set_irq_funcs()
9414 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; in gfx_v10_0_set_irq_funcs()
9416 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; in gfx_v10_0_set_irq_funcs()
9417 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; in gfx_v10_0_set_irq_funcs()
9419 adev->gfx.priv_reg_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
9420 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; in gfx_v10_0_set_irq_funcs()
9422 adev->gfx.priv_inst_irq.num_types = 1; in gfx_v10_0_set_irq_funcs()
9423 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; in gfx_v10_0_set_irq_funcs()
9440 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; in gfx_v10_0_set_rlc_funcs()
9444 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; in gfx_v10_0_set_rlc_funcs()
9453 unsigned total_cu = adev->gfx.config.max_cu_per_sh * in gfx_v10_0_set_gds_init()
9454 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
9455 adev->gfx.config.max_shader_engines; in gfx_v10_0_set_gds_init()
9494 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); in gfx_v10_0_get_wgp_active_bitmap_per_sh()
9542 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v10_0_get_cu_info()
9543 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
9544 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
9561 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v10_0_get_cu_info()
9563 if (counter < adev->gfx.config.max_cu_per_sh) in gfx_v10_0_get_cu_info()
9597 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v10_3_get_disabled_sa()
9598 adev->gfx.config.max_shader_engines); in gfx_v10_3_get_disabled_sa()
9612 max_sa_per_se = adev->gfx.config.max_sh_per_se; in gfx_v10_3_program_pbb_mode()
9614 max_shader_engines = adev->gfx.config.max_shader_engines; in gfx_v10_3_program_pbb_mode()