Lines Matching refs:VMID
1994 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache()
2038 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache()
2113 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2194 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2235 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2317 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2353 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2359 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2718 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2799 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
2936 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3018 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3449 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3455 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3568 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v11_0_gfx_mqd_init()
3575 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v11_0_gfx_mqd_init()
3845 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v11_0_compute_mqd_init()