Lines Matching refs:mqd
3553 struct v11_gfx_mqd *mqd = m; in gfx_v11_0_gfx_mqd_init() local
3559 mqd->cp_gfx_hqd_wptr = 0; in gfx_v11_0_gfx_mqd_init()
3560 mqd->cp_gfx_hqd_wptr_hi = 0; in gfx_v11_0_gfx_mqd_init()
3563 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3564 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v11_0_gfx_mqd_init()
3571 mqd->cp_gfx_mqd_control = tmp; in gfx_v11_0_gfx_mqd_init()
3576 mqd->cp_gfx_hqd_vmid = 0; in gfx_v11_0_gfx_mqd_init()
3582 mqd->cp_gfx_hqd_queue_priority = tmp; in gfx_v11_0_gfx_mqd_init()
3587 mqd->cp_gfx_hqd_quantum = tmp; in gfx_v11_0_gfx_mqd_init()
3591 mqd->cp_gfx_hqd_base = hqd_gpu_addr; in gfx_v11_0_gfx_mqd_init()
3592 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v11_0_gfx_mqd_init()
3596 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3597 mqd->cp_gfx_hqd_rptr_addr_hi = in gfx_v11_0_gfx_mqd_init()
3602 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3603 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
3613 mqd->cp_gfx_hqd_cntl = tmp; in gfx_v11_0_gfx_mqd_init()
3625 mqd->cp_rb_doorbell_control = tmp; in gfx_v11_0_gfx_mqd_init()
3628 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); in gfx_v11_0_gfx_mqd_init()
3631 mqd->cp_gfx_hqd_active = 1; in gfx_v11_0_gfx_mqd_init()
3640 struct v11_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_gfx_queue_init_register() local
3643 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); in gfx_v11_0_gfx_queue_init_register()
3644 WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); in gfx_v11_0_gfx_queue_init_register()
3647 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); in gfx_v11_0_gfx_queue_init_register()
3648 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in gfx_v11_0_gfx_queue_init_register()
3651 WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); in gfx_v11_0_gfx_queue_init_register()
3654 WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); in gfx_v11_0_gfx_queue_init_register()
3657 mqd->cp_gfx_hqd_queue_priority); in gfx_v11_0_gfx_queue_init_register()
3658 WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); in gfx_v11_0_gfx_queue_init_register()
3661 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); in gfx_v11_0_gfx_queue_init_register()
3662 WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); in gfx_v11_0_gfx_queue_init_register()
3665 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); in gfx_v11_0_gfx_queue_init_register()
3666 WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); in gfx_v11_0_gfx_queue_init_register()
3669 WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); in gfx_v11_0_gfx_queue_init_register()
3672 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); in gfx_v11_0_gfx_queue_init_register()
3673 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); in gfx_v11_0_gfx_queue_init_register()
3676 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); in gfx_v11_0_gfx_queue_init_register()
3679 WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); in gfx_v11_0_gfx_queue_init_register()
3688 struct v11_gfx_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_gfx_init_queue() local
3692 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3702 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3706 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_gfx_init_queue()
3791 struct v11_compute_mqd *mqd = m; in gfx_v11_0_compute_mqd_init() local
3795 mqd->header = 0xC0310800; in gfx_v11_0_compute_mqd_init()
3796 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v11_0_compute_mqd_init()
3797 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
3798 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
3799 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
3800 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
3801 mqd->compute_misc_reserved = 0x00000007; in gfx_v11_0_compute_mqd_init()
3804 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; in gfx_v11_0_compute_mqd_init()
3805 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in gfx_v11_0_compute_mqd_init()
3812 mqd->cp_hqd_eop_control = tmp; in gfx_v11_0_compute_mqd_init()
3831 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v11_0_compute_mqd_init()
3834 mqd->cp_hqd_dequeue_request = 0; in gfx_v11_0_compute_mqd_init()
3835 mqd->cp_hqd_pq_rptr = 0; in gfx_v11_0_compute_mqd_init()
3836 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v11_0_compute_mqd_init()
3837 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v11_0_compute_mqd_init()
3840 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
3841 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); in gfx_v11_0_compute_mqd_init()
3846 mqd->cp_mqd_control = tmp; in gfx_v11_0_compute_mqd_init()
3850 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v11_0_compute_mqd_init()
3851 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v11_0_compute_mqd_init()
3863 mqd->cp_hqd_pq_control = tmp; in gfx_v11_0_compute_mqd_init()
3867 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
3868 mqd->cp_hqd_pq_rptr_report_addr_hi = in gfx_v11_0_compute_mqd_init()
3873 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
3874 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
3891 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v11_0_compute_mqd_init()
3894 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); in gfx_v11_0_compute_mqd_init()
3897 mqd->cp_hqd_vmid = 0; in gfx_v11_0_compute_mqd_init()
3901 mqd->cp_hqd_persistent_state = tmp; in gfx_v11_0_compute_mqd_init()
3906 mqd->cp_hqd_ib_control = tmp; in gfx_v11_0_compute_mqd_init()
3909 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; in gfx_v11_0_compute_mqd_init()
3910 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; in gfx_v11_0_compute_mqd_init()
3912 mqd->cp_hqd_active = prop->hqd_active; in gfx_v11_0_compute_mqd_init()
3920 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kiq_init_register() local
3932 mqd->cp_hqd_eop_base_addr_lo); in gfx_v11_0_kiq_init_register()
3934 mqd->cp_hqd_eop_base_addr_hi); in gfx_v11_0_kiq_init_register()
3938 mqd->cp_hqd_eop_control); in gfx_v11_0_kiq_init_register()
3942 mqd->cp_hqd_pq_doorbell_control); in gfx_v11_0_kiq_init_register()
3953 mqd->cp_hqd_dequeue_request); in gfx_v11_0_kiq_init_register()
3955 mqd->cp_hqd_pq_rptr); in gfx_v11_0_kiq_init_register()
3957 mqd->cp_hqd_pq_wptr_lo); in gfx_v11_0_kiq_init_register()
3959 mqd->cp_hqd_pq_wptr_hi); in gfx_v11_0_kiq_init_register()
3964 mqd->cp_mqd_base_addr_lo); in gfx_v11_0_kiq_init_register()
3966 mqd->cp_mqd_base_addr_hi); in gfx_v11_0_kiq_init_register()
3970 mqd->cp_mqd_control); in gfx_v11_0_kiq_init_register()
3974 mqd->cp_hqd_pq_base_lo); in gfx_v11_0_kiq_init_register()
3976 mqd->cp_hqd_pq_base_hi); in gfx_v11_0_kiq_init_register()
3980 mqd->cp_hqd_pq_control); in gfx_v11_0_kiq_init_register()
3984 mqd->cp_hqd_pq_rptr_report_addr_lo); in gfx_v11_0_kiq_init_register()
3986 mqd->cp_hqd_pq_rptr_report_addr_hi); in gfx_v11_0_kiq_init_register()
3990 mqd->cp_hqd_pq_wptr_poll_addr_lo); in gfx_v11_0_kiq_init_register()
3992 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v11_0_kiq_init_register()
4003 mqd->cp_hqd_pq_doorbell_control); in gfx_v11_0_kiq_init_register()
4007 mqd->cp_hqd_pq_wptr_lo); in gfx_v11_0_kiq_init_register()
4009 mqd->cp_hqd_pq_wptr_hi); in gfx_v11_0_kiq_init_register()
4012 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v11_0_kiq_init_register()
4015 mqd->cp_hqd_persistent_state); in gfx_v11_0_kiq_init_register()
4019 mqd->cp_hqd_active); in gfx_v11_0_kiq_init_register()
4030 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kiq_init_queue() local
4038 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4050 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4061 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4070 struct v11_compute_mqd *mqd = ring->mqd_ptr; in gfx_v11_0_kcq_init_queue() local
4074 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4082 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4086 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()