Lines Matching refs:rlc
2020 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_cp_gfx_start()
2342 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; in gfx_v6_0_rlc_init()
2343 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2346 adev->gfx.rlc.cs_data = si_cs_data; in gfx_v6_0_rlc_init()
2347 src_ptr = adev->gfx.rlc.reg_list; in gfx_v6_0_rlc_init()
2348 dws = adev->gfx.rlc.reg_list_size; in gfx_v6_0_rlc_init()
2349 cs_data = adev->gfx.rlc.cs_data; in gfx_v6_0_rlc_init()
2360 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); in gfx_v6_0_rlc_init()
2361 dws = adev->gfx.rlc.clear_state_size + (256 / 4); in gfx_v6_0_rlc_init()
2366 &adev->gfx.rlc.clear_state_obj, in gfx_v6_0_rlc_init()
2367 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v6_0_rlc_init()
2368 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v6_0_rlc_init()
2376 dst_ptr = adev->gfx.rlc.cs_ptr; in gfx_v6_0_rlc_init()
2377 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; in gfx_v6_0_rlc_init()
2380 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); in gfx_v6_0_rlc_init()
2382 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); in gfx_v6_0_rlc_init()
2383 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); in gfx_v6_0_rlc_init()
2416 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) in gfx_v6_0_update_rlc() argument
2421 if (tmp != rlc) in gfx_v6_0_update_rlc()
2422 WREG32(mmRLC_CNTL, rlc); in gfx_v6_0_update_rlc()
2492 adev->gfx.rlc.funcs->stop(adev); in gfx_v6_0_rlc_resume()
2493 adev->gfx.rlc.funcs->reset(adev); in gfx_v6_0_rlc_resume()
2521 adev->gfx.rlc.funcs->start(adev); in gfx_v6_0_rlc_resume()
2787 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2789 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_gfx_cgpg()
2811 if (adev->gfx.rlc.cs_data == NULL) in gfx_v6_0_get_csb_size()
2819 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_get_csb_size()
2844 if (adev->gfx.rlc.cs_data == NULL) in gfx_v6_0_get_csb_buffer()
2855 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_get_csb_buffer()
2895 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_pg()
2896 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
2903 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v6_0_init_pg()
2904 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); in gfx_v6_0_init_pg()
3035 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; in gfx_v6_0_early_init()
3066 r = adev->gfx.rlc.funcs->init(adev); in gfx_v6_0_sw_init()
3132 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v6_0_hw_init()
3150 adev->gfx.rlc.funcs->stop(adev); in gfx_v6_0_hw_fini()