Lines Matching refs:RREG32
1591 data = RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1592 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_get_rb_active_bitmap()
1795 RREG32(mmCC_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1797 RREG32(mmGC_USER_RB_BACKEND_DISABLE); in gfx_v7_0_setup_rb()
1799 RREG32(mmPA_SC_RASTER_CONFIG); in gfx_v7_0_setup_rb()
1801 RREG32(mmPA_SC_RASTER_CONFIG_1); in gfx_v7_0_setup_rb()
1957 tmp = RREG32(mmSPI_CONFIG_CNTL); in gfx_v7_0_constants_init()
1965 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff; in gfx_v7_0_constants_init()
1969 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c; in gfx_v7_0_constants_init()
1973 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000; in gfx_v7_0_constants_init()
2006 tmp = RREG32(mmSPI_ARB_PRIORITY); in gfx_v7_0_constants_init()
2046 tmp = RREG32(mmSCRATCH_REG0); in gfx_v7_0_ring_test_ring()
2321 tmp = RREG32(mmSCRATCH_REG0); in gfx_v7_0_ring_test_ib()
2596 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2604 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
2821 tmp = RREG32(mmCP_HPD_EOP_CONTROL); in gfx_v7_0_compute_pipe_init()
2835 if (RREG32(mmCP_HQD_ACTIVE) & 1) { in gfx_v7_0_mqd_deactivate()
2838 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) in gfx_v7_0_mqd_deactivate()
2873 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
2884 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); in gfx_v7_0_mqd_init()
2893 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2928 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v7_0_mqd_init()
2947 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
2953 mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL); in gfx_v7_0_mqd_init()
2954 mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR); in gfx_v7_0_mqd_init()
2955 mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI); in gfx_v7_0_mqd_init()
2956 mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR); in gfx_v7_0_mqd_init()
2957 mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE); in gfx_v7_0_mqd_init()
2958 mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD); in gfx_v7_0_mqd_init()
2959 mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE); in gfx_v7_0_mqd_init()
2960 mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO); in gfx_v7_0_mqd_init()
2961 mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI); in gfx_v7_0_mqd_init()
2962 mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO); in gfx_v7_0_mqd_init()
2963 mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI); in gfx_v7_0_mqd_init()
2964 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); in gfx_v7_0_mqd_init()
2965 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); in gfx_v7_0_mqd_init()
2966 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY); in gfx_v7_0_mqd_init()
2967 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY); in gfx_v7_0_mqd_init()
2968 mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR); in gfx_v7_0_mqd_init()
2984 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); in gfx_v7_0_mqd_commit()
3045 tmp = RREG32(mmCP_CPF_DEBUG); in gfx_v7_0_cp_compute_resume()
3096 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_enable_gui_idle_interrupt()
3288 tmp = RREG32(mmRLC_LB_CNTL); in gfx_v7_0_enable_lbpw()
3306 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3320 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in gfx_v7_0_wait_for_rlc_serdes()
3330 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3339 orig = data = RREG32(mmRLC_CNTL); in gfx_v7_0_halt_rlc()
3348 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0) in gfx_v7_0_halt_rlc()
3374 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask) in gfx_v7_0_set_safe_mode()
3380 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0) in gfx_v7_0_set_safe_mode()
3428 u32 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_rlc_reset()
3466 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3511 data = RREG32(mmRLC_SPM_VMID); in gfx_v7_0_update_spm_vmid()
3525 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v7_0_enable_cgcg()
3551 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3552 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3553 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3554 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3571 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3578 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
3598 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3613 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); in gfx_v7_0_enable_mgcg()
3618 data = RREG32(mmRLC_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3624 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3630 orig = data = RREG32(mmCGTS_SM_CTRL_REG); in gfx_v7_0_enable_mgcg()
3669 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pu()
3683 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_sclk_slowdown_on_pd()
3696 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_cp_pg()
3709 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gds_pg()
3732 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3737 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
3742 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_cgpg()
3747 orig = data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_enable_gfx_cgpg()
3752 data = RREG32(mmDB_RENDER_CONTROL); in gfx_v7_0_enable_gfx_cgpg()
3774 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
3775 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); in gfx_v7_0_get_cu_active_bitmap()
3791 tmp = RREG32(mmRLC_MAX_PG_CU); in gfx_v7_0_init_ao_cu_mask()
3802 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_static_mgpg()
3816 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_enable_gfx_dynamic_mgpg()
3849 orig = data = RREG32(mmRLC_PG_CNTL); in gfx_v7_0_init_gfx_cgpg()
3857 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
3865 data = RREG32(mmRLC_PG_DELAY_2); in gfx_v7_0_init_gfx_cgpg()
3870 data = RREG32(mmRLC_AUTO_PG_CTRL); in gfx_v7_0_init_gfx_cgpg()
4032 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | in gfx_v7_0_get_gpu_clock_counter()
4033 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in gfx_v7_0_get_gpu_clock_counter()
4096 return RREG32(mmSQ_IND_DATA); in wave_read_ind()
4111 *(out++) = RREG32(mmSQ_IND_DATA); in wave_read_regs()
4289 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); in gfx_v7_0_gpu_early_init()
4301 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_early_init()
4305 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); in gfx_v7_0_gpu_early_init()
4558 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) in gfx_v7_0_is_idle()
4572 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK; in gfx_v7_0_wait_for_idle()
4588 tmp = RREG32(mmGRBM_STATUS); in gfx_v7_0_soft_reset()
4604 tmp = RREG32(mmGRBM_STATUS2); in gfx_v7_0_soft_reset()
4609 tmp = RREG32(mmSRBM_STATUS); in gfx_v7_0_soft_reset()
4628 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4632 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4638 tmp = RREG32(mmGRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4642 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4646 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4652 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
4667 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4672 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state()
4718 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4723 mec_int_cntl = RREG32(mec_int_cntl_reg); in gfx_v7_0_set_compute_eop_interrupt_state()
4741 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4746 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state()
4766 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
4771 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_inst_fault_state()
5087 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE); in gfx_v7_0_set_gds_init()
5090 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID); in gfx_v7_0_set_gds_init()