Lines Matching refs:simd
4089 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4093 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
4099 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
4105 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
4114 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint3… in gfx_v7_0_read_wave_data() argument
4118 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4119 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4120 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4121 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4122 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
4123 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v7_0_read_wave_data()
4124 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v7_0_read_wave_data()
4125 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); in gfx_v7_0_read_wave_data()
4126 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v7_0_read_wave_data()
4127 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); in gfx_v7_0_read_wave_data()
4128 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); in gfx_v7_0_read_wave_data()
4129 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); in gfx_v7_0_read_wave_data()
4130 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); in gfx_v7_0_read_wave_data()
4131 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); in gfx_v7_0_read_wave_data()
4132 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); in gfx_v7_0_read_wave_data()
4133 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); in gfx_v7_0_read_wave_data()
4134 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); in gfx_v7_0_read_wave_data()
4135 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v7_0_read_wave_data()
4136 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v7_0_read_wave_data()
4139 static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, in gfx_v7_0_read_wave_sgprs() argument
4144 adev, simd, wave, 0, in gfx_v7_0_read_wave_sgprs()