Lines Matching refs:mqd
3207 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) in gfx_v9_0_mqd_set_priority() argument
3213 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; in gfx_v9_0_mqd_set_priority()
3214 mqd->cp_hqd_queue_priority = in gfx_v9_0_mqd_set_priority()
3223 struct v9_mqd *mqd = ring->mqd_ptr; in gfx_v9_0_mqd_init() local
3227 mqd->header = 0xC0310800; in gfx_v9_0_mqd_init()
3228 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v9_0_mqd_init()
3229 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v9_0_mqd_init()
3230 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v9_0_mqd_init()
3231 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v9_0_mqd_init()
3232 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v9_0_mqd_init()
3233 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; in gfx_v9_0_mqd_init()
3234 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; in gfx_v9_0_mqd_init()
3235 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; in gfx_v9_0_mqd_init()
3236 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; in gfx_v9_0_mqd_init()
3237 mqd->compute_misc_reserved = 0x00000003; in gfx_v9_0_mqd_init()
3239 mqd->dynamic_cu_mask_addr_lo = in gfx_v9_0_mqd_init()
3242 mqd->dynamic_cu_mask_addr_hi = in gfx_v9_0_mqd_init()
3247 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; in gfx_v9_0_mqd_init()
3248 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in gfx_v9_0_mqd_init()
3255 mqd->cp_hqd_eop_control = tmp; in gfx_v9_0_mqd_init()
3274 mqd->cp_hqd_pq_doorbell_control = tmp; in gfx_v9_0_mqd_init()
3278 mqd->cp_hqd_dequeue_request = 0; in gfx_v9_0_mqd_init()
3279 mqd->cp_hqd_pq_rptr = 0; in gfx_v9_0_mqd_init()
3280 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v9_0_mqd_init()
3281 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v9_0_mqd_init()
3284 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; in gfx_v9_0_mqd_init()
3285 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in gfx_v9_0_mqd_init()
3290 mqd->cp_mqd_control = tmp; in gfx_v9_0_mqd_init()
3294 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v9_0_mqd_init()
3295 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v9_0_mqd_init()
3310 mqd->cp_hqd_pq_control = tmp; in gfx_v9_0_mqd_init()
3314 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v9_0_mqd_init()
3315 mqd->cp_hqd_pq_rptr_report_addr_hi = in gfx_v9_0_mqd_init()
3320 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v9_0_mqd_init()
3321 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v9_0_mqd_init()
3325 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); in gfx_v9_0_mqd_init()
3328 mqd->cp_hqd_vmid = 0; in gfx_v9_0_mqd_init()
3332 mqd->cp_hqd_persistent_state = tmp; in gfx_v9_0_mqd_init()
3337 mqd->cp_hqd_ib_control = tmp; in gfx_v9_0_mqd_init()
3340 gfx_v9_0_mqd_set_priority(ring, mqd); in gfx_v9_0_mqd_init()
3341 mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM); in gfx_v9_0_mqd_init()
3347 mqd->cp_hqd_active = 1; in gfx_v9_0_mqd_init()
3355 struct v9_mqd *mqd = ring->mqd_ptr; in gfx_v9_0_kiq_init_register() local
3362 mqd->cp_hqd_eop_base_addr_lo); in gfx_v9_0_kiq_init_register()
3364 mqd->cp_hqd_eop_base_addr_hi); in gfx_v9_0_kiq_init_register()
3368 mqd->cp_hqd_eop_control); in gfx_v9_0_kiq_init_register()
3372 mqd->cp_hqd_pq_doorbell_control); in gfx_v9_0_kiq_init_register()
3383 mqd->cp_hqd_dequeue_request); in gfx_v9_0_kiq_init_register()
3385 mqd->cp_hqd_pq_rptr); in gfx_v9_0_kiq_init_register()
3387 mqd->cp_hqd_pq_wptr_lo); in gfx_v9_0_kiq_init_register()
3389 mqd->cp_hqd_pq_wptr_hi); in gfx_v9_0_kiq_init_register()
3394 mqd->cp_mqd_base_addr_lo); in gfx_v9_0_kiq_init_register()
3396 mqd->cp_mqd_base_addr_hi); in gfx_v9_0_kiq_init_register()
3400 mqd->cp_mqd_control); in gfx_v9_0_kiq_init_register()
3404 mqd->cp_hqd_pq_base_lo); in gfx_v9_0_kiq_init_register()
3406 mqd->cp_hqd_pq_base_hi); in gfx_v9_0_kiq_init_register()
3410 mqd->cp_hqd_pq_control); in gfx_v9_0_kiq_init_register()
3414 mqd->cp_hqd_pq_rptr_report_addr_lo); in gfx_v9_0_kiq_init_register()
3416 mqd->cp_hqd_pq_rptr_report_addr_hi); in gfx_v9_0_kiq_init_register()
3420 mqd->cp_hqd_pq_wptr_poll_addr_lo); in gfx_v9_0_kiq_init_register()
3422 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v9_0_kiq_init_register()
3442 mqd->cp_hqd_pq_doorbell_control); in gfx_v9_0_kiq_init_register()
3446 mqd->cp_hqd_pq_wptr_lo); in gfx_v9_0_kiq_init_register()
3448 mqd->cp_hqd_pq_wptr_hi); in gfx_v9_0_kiq_init_register()
3451 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v9_0_kiq_init_register()
3454 mqd->cp_hqd_persistent_state); in gfx_v9_0_kiq_init_register()
3458 mqd->cp_hqd_active); in gfx_v9_0_kiq_init_register()
3508 struct v9_mqd *mqd = ring->mqd_ptr; in gfx_v9_0_kiq_init_queue() local
3523 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3535 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3536 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; in gfx_v9_0_kiq_init_queue()
3537 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; in gfx_v9_0_kiq_init_queue()
3548 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kiq_init_queue()
3557 struct v9_mqd *mqd = ring->mqd_ptr; in gfx_v9_0_kcq_init_queue() local
3568 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3569 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; in gfx_v9_0_kcq_init_queue()
3570 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; in gfx_v9_0_kcq_init_queue()
3578 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()
3582 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); in gfx_v9_0_kcq_init_queue()